Toward Multi-Gigabit Wireless: Design of High-Throughput MIMO Detectors With Hardware-Efficient Architecture

This paper presents a hardware-efficient architecture for 4×4 and 8×8 high-throughput MIMO detectors. The adopted non-constant K-best algorithm tends to keep more survival nodes in top search tree layers and reduce computational complexity in bottom layers as opposed to the conventional K-best algorithm. A pipelined architecture is used to generate one detection output per clock cycle, thus meeting multi-gigabit throughput requirements for advanced wireless communication systems. The proposed efficient folding scheme strikes a suitable balance between complexity and throughput. This paper also presents a discussion on the scalability of this architecture with respect to the setting of QAM size, K values, and antenna number. One 4×4 MIMO detector IC has been manufactured and one 8×8 MIMO detector layout has been realized, both in 90-nm CMOS technology. The 4×4 detector IC has 232 kilogates (KG). Its maximum measured throughput is 4.08 Gbps at 170-MHz operating frequency and 1.3-V core voltage. The 8×8 detector has 665 KG. Its post-layout simulation results show that it achieves 4.37-Gbps throughput at 182-MHz operating frequency and 0.9-V core voltage. Compared to earlier hard-output detectors, both implemented detectors demonstrate good normalized power and normalized hardware efficiencies.

[1]  P. Glenn Gulak,et al.  A 0.13µm CMOS 655Mb/s 4×4 64-QAM K-Best MIMO detector , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  Wai Ho Mow,et al.  A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[3]  Pei-Yun Tsai,et al.  A 4×4 64-QAM reduced-complexity K-best MIMO detector up to 1.5Gbps , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[4]  Mahdi Shabany,et al.  Ultra high-throughput architectures for hard-output MIMO detectors in the complex domain , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[5]  Claus-Peter Schnorr,et al.  Lattice basis reduction: Improved practical algorithms and solving subset sum problems , 1991, FCT.

[6]  Hsi-Pin Ma,et al.  A Power-Efficient Configurable Low-Complexity MIMO Detector , 2009, IEEE Trans. Circuits Syst. I Regul. Pap..

[7]  Xi Chen,et al.  VLSI Implementation of a High-Throughput Iterative Fixed-Complexity Sphere Decoder , 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

[8]  Giuseppe Caire,et al.  A unified framework for tree search decoding: rediscovering the sequential decoder , 2005, IEEE 6th Workshop on Signal Processing Advances in Wireless Communications, 2005..

[9]  A. Burg,et al.  VLSI implementation of MIMO detection using the sphere decoding algorithm , 2005, IEEE Journal of Solid-State Circuits.

[10]  A. Burg,et al.  VLSI implementation of the sphere decoding algorithm , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[11]  Neil Genzlinger.  A. and Q , 2006 .

[12]  Ahmed M. Eltawil,et al.  Design and Implementation of a Sort-Free K-Best Sphere Decoder , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Gerard J. Foschini,et al.  Layered space-time architecture for wireless communication in a fading environment when using multi-element antennas , 1996, Bell Labs Technical Journal.

[14]  W. Marsden.  I and J , 2012 .

[15]  Antonia Maria Tulino,et al.  Random Matrix Theory and Wireless Communications , 2004, Found. Trends Commun. Inf. Theory.

[16]  Dejan Markovic,et al.  A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS , 2009, 2009 Proceedings of ESSCIRC.

[17]  J.R. Fonollosa,et al.  Efficient implementation of sphere demodulation , 2003, 2003 4th IEEE Workshop on Signal Processing Advances in Wireless Communications - SPAWC 2003 (IEEE Cat. No.03EX689).

[18]  U. Fincke,et al.  Improved methods for calculating vectors of short length in a lattice , 1985 .

[19]  Liang Liu,et al.  Area-Efficient Configurable High-Throughput Signal Detector Supporting Multiple MIMO Modes , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[20]  Mojtaba Mahdavi,et al.  Novel MIMO Detection Algorithm for High-Order Constellations in the Complex Domain , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[21]  Andreas Peter Burg,et al.  K-best MIMO detection VLSI architectures achieving up to 424 Mbps , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[22]  P. Glenn Gulak,et al.  A 675 Mbps, 4 × 4 64-QAM K-Best MIMO Detector in 0.13 µm CMOS , 2012, IEEE Trans. Very Large Scale Integr. Syst..

[23]  Tong Zhang,et al.  A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- $\mu\hbox{m}$ CMOS Technology , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[24]  Tzi-Dar Chiueh,et al.  A 74.8 mW Soft-Output Detector IC for 8 $\,\times\,$8 Spatial-Multiplexing MIMO Communications , 2010, IEEE Journal of Solid-State Circuits.

[25]  Dejan Markovic,et al.  A Flexible DSP Architecture for MIMO Sphere Decoding , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[26]  L. G. Barbero,et al.  A Fixed-Complexity MIMO Detector Based on the Complex Sphere Decoder , 2006, 2006 IEEE 7th Workshop on Signal Processing Advances in Wireless Communications.

[27]  Zhan Guo,et al.  Algorithm and implementation of the K-best sphere decoding for MIMO detection , 2006, IEEE Journal on Selected Areas in Communications.