Analog-to-Digital Converter-Based Serial Links: An Overview

The ever-increasing number of networked devices and cloud computing applications has created dramatic growth in data center traffic. This necessitates that the serial links that perform the communication between ICs in these systems must operate at higher per-channel data rates, with proposed Ethernet and Optical Internetworking Forum standards supporting 56 Gb/s and scaling beyond 100 Gb/s in the future. However, the large amount of frequency-dependent loss present in conventional electrical channels makes the use of common two-level pulse amplitude modulation (PAM-2) challenging without significant infrastructure upgrades. This motivates the use of the more spectrally efficient four-level PAM (PAM-4). While PAM-4 has a Nyquist frequency half of PAM-2, it is more sensitive to residual intersymbol interference (ISI). Thus, receiver front ends often employ large tap-count feed-forward equalizers (FFEs) that are difficult to robustly implement in the analog domain due to process, voltage, and temperature variations.

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