Performance-driven soft-macro clustering and placement by preserving HDL design hierarchy

In this paper, we present a performance-driven soft-macro clustering and placement method which preserves HDL design hierarchy to guide the soft-macro placement process. We also present a complete chip design methodology by integrating the proposed method and a set of commercial EDA tools. Experiments on three industrial designs ranging from 75K to 230K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delay on an average of 24%.

[1]  Chung-Kuan Cheng,et al.  Ratio cut partitioning for hierarchical designs , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  F. Brglez,et al.  Circuit partitioning for logic synthesis , 1991 .

[3]  Edward Sciore,et al.  A method for automatic rule derivation to support semantic query optimization , 1992, TODS.

[4]  Raul Camposano.  The quarter micron challenge: intergrating physical and logic design , 1997, ISPD '97.

[5]  S. Grout,et al.  Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century , 1997, ISPD '97.

[6]  Wojciech Ziarko,et al.  The Discovery, Analysis, and Representation of Data Dependencies in Databases , 1991, Knowledge Discovery in Databases.

[7]  Qiming Chen,et al.  Using type inference and induced rules to provide intensional answers , 1991, [1991] Proceedings. Seventh International Conference on Data Engineering.

[8]  Naveed A. Sherwani,et al.  Algorithms for VLSI Physical Design Automation , 1999, Springer US.

[9]  Jerzy W. Grzymala-Busse,et al.  Rough Sets , 1995, Commun. ACM.

[10]  Tomasz Imielinski,et al.  An Interval Classifier for Database Mining Applications , 1992, VLDB.

[11]  Tomasz Imielinski,et al.  Mining association rules between sets of items in large databases , 1993, SIGMOD Conference.

[12]  Andrew B. Kahng,et al.  Recent directions in netlist partitioning , 1995 .

[13]  Ryszard S. Michalski,et al.  A Theory and Methodology of Inductive Learning , 1983, Artificial Intelligence.

[14]  Jason Cong,et al.  Exploiting signal flow and logic dependency in standard cell placement , 1995, ASP-DAC '95.

[15]  Narendra V. Shenoy,et al.  The future of logic synthesis and physical design in deep-submicron process geometries , 1997, ISPD '97.

[16]  Tomasz Imielinski,et al.  Intelligent Query Answering in Rule Based Systems , 1988, J. Log. Program..

[17]  Jack Minker,et al.  Semantic Query Optimization in Expert Systems and Database Systems , 1984, Expert Database Workshop.

[18]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[19]  Clement T. Yu,et al.  Automatic Knowledge Acquisition and Maintenance for Semantic Query Optimization , 1989, IEEE Trans. Knowl. Data Eng..

[20]  G. Saucier,et al.  Partitioning with cone structures , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[21]  Ernest S. Kuh.  Physical design: reminiscing and looking ahead , 1997, ISPD '97.

[22]  Jiawei Han,et al.  Data-Driven Discovery of Quantitative Rules in Relational Databases , 1993, IEEE Trans. Knowl. Data Eng..

[23]  Thomas Lengauer,et al.  Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.

[24]  Ernst G. Ulrich,et al.  Clustering and linear placement , 1972, DAC '72.

[25]  Youn-Long Lin,et al.  Preserving HDL synthesis hierarchy for cell placement , 1997, ISPD '97.

[26]  Youn-Long Lin,et al.  A row-based cell placement method that utilizes circuit structural properties , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[27]  Neil R. Quinn.  The placement problem as viewed from the physics of classical mechanics , 1975, DAC '75.

[28]  Gotaro Odawara,et al.  Partitioning and Placement Technique for CMOS Gate Arrays , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.