Daily scheduling of multi-pass lots at assembly and test facilities

In semiconductor manufacturing, wafers are grouped into lots and sent to a separate facility for assembly and test before being shipped to the customer. This paper investigates the daily scheduling of such lots in a re-entrant flow environment where it is necessary to plan for several passes of the same lot through the system. Up to a dozen operations are required during assembly and test and many are performed by the same equipment. Work in process lots that have more than a single step remaining in their route are referred to as multi-pass lots. The scheduling problem is to determine machine setups, lot assignments, and lot sequences to achieve optimal output, as measured by four objectives related to key device shortages, throughput, machine utilisation, and makespan, in that order. When more than a single pass is considered, it is not possible to develop an efficient mathematical model to represent the decision process. To find solutions, we take a multi-stage approach, first applying a reactive greedy randomised search procedure (GRASP) to develop a schedule for the current lots waiting to be processed, and then using a similar procedure to schedule additional passes and changeovers. The performance of the methodology is evaluated using data provided by a leading semiconductor manufacturer for instances with up to 36 machines, 284 tooling pieces from six families, and 1036 lots. The results indicate that, on average, multi-pass scheduling improves the weighted sum of lots processed by 40% and machine utilisation by 11% compared to the results obtained with the single-pass algorithm.