Characterization and modeling of dynamic variability induced by BTI in nano-scaled transistors

Abstract In this paper, dynamic variability (DV) induced by BTI is deeply investigated in nano-scaled devices by means of statistical measurements and modeling. The impact of a single charge q on Vt is first investigated through 3D electrostatic simulations. In planar devices, this MC modeling allows proving that the average Vt shift induced by a single q denoted ηt is inversely proportional to the device area. In trigate 3D transistors, BTI trapping not only occurs at the top surface (TS) oxide but also at the device sidewalls (SW). For Πfet Nanowire, this implies that ηt exhibits a complex variation with device scaling unlike in planar structures. In contrast, Finfet rather behaves as a vertical planar device for which SW plays now the role of TS. Finally the impact of device scaling on NBTI degradation is thoroughly studied in 3D technologies. Enhanced NBTI is measured on narrower devices. This phenomenon is well explained and reproduced by 3D MC simulations considering a poorer quality of the SW gate oxide with respect to its TS counterpart.

[1]  T. Numata,et al.  Performance, variability and reliability of silicon tri-gate nanowire MOSFETs , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[2]  O. Faynot,et al.  Scaling of Ω-gate SOI nanowire N- and P-FET down to 10nm gate length: Size- and orientation-dependent strain effects , 2013, 2013 Symposium on VLSI Technology.

[3]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[4]  T. Grasser,et al.  Statistics of Multiple Trapped Charges in the Gate Oxide of Deeply Scaled MOSFET Devices—Application to NBTI , 2010, IEEE Electron Device Letters.

[5]  Gilles Reimbold,et al.  A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology , 2014, IEEE Transactions on Electron Devices.

[6]  Byoung Hun Lee,et al.  Process-Dependent N/PBTI Characteristics of TiN Gate FinFETs , 2012, IEEE Electron Device Letters.

[7]  G. Ghibaudo,et al.  Impact of Single Charge Trapping on the Variability of Ultrascaled Planar and Trigate FDSOI MOSFETs: Experiment Versus Simulation , 2013, IEEE Transactions on Electron Devices.

[8]  A. Asenov,et al.  Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs , 2006, IEEE Transactions on Electron Devices.

[9]  Donggun Park,et al.  A study of negative-bias temperature instability of SOI and body-tied FinFETs , 2005 .

[10]  A. Asenov,et al.  PBTI/NBTI-Related Variability in TB-SOI and DG MOSFETs , 2010, IEEE Electron Device Letters.

[11]  M. Orlowski,et al.  Carrier transport near the Si/SiO2 interface of a MOSFET , 1989 .

[12]  O. Faynot,et al.  New insight on the geometry dependence of BTI in 3D technologies based on experiments and modeling , 2017, 2017 Symposium on VLSI Technology.

[14]  Gilles Reimbold,et al.  Modeling the Dynamic Variability Induced by Charged Traps in a Bilayer Gate Oxide , 2015, IEEE Transactions on Electron Devices.

[15]  Dimitri Linten,et al.  The defect-centric perspective of device and circuit reliability—From gate oxide defects to circuits , 2016 .

[16]  G. Ghibaudo,et al.  Extensive study of Bias Temperature Instability in nanowire transistors , 2015 .

[17]  Andrew R. Brown,et al.  Simulation of statistical aspects of reliability in nano CMOS transistors , 2009, 2009 IEEE International Integrated Reliability Workshop Final Report.

[18]  Asen Asenov,et al.  3-D Statistical Simulation Comparison of Oxide Reliability of Planar MOSFETs and FinFET , 2013, IEEE Transactions on Electron Devices.

[19]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[20]  B. Kaczer,et al.  Recent advances in understanding the bias temperature instability , 2010, 2010 International Electron Devices Meeting.