An improved RNS generator 2n ± k based on threshold logic

This paper presents a new scheme for designing residue generators using threshold logic. This approach is based on the periodicity of the series of powers of 2 taken modulo 2n ± k. In addition, a new algorithm is proposed to obtain a new set of partitions which are more advantageous in terms of area and delay for the presented topology. Experimental results in the analized range of k and n show that new proposed circuits using the novel partitioning are 70% faster and provide area savings of 64%, when compared with similar circuits using the partitioning methods presented to date.

[1]  Stanislaw J. Piestrak Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders , 1994, IEEE Trans. Computers.

[2]  Gian Carlo Cardarilli,et al.  Reducing power dissipation in FIR filters using the residue number system , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[3]  Stamatis Vassiliadis,et al.  Periodic symmetric functions, serial addition, and multiplication with neural networks , 1998, IEEE Trans. Neural Networks.

[4]  R. Capocelli,et al.  Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa , 1988 .

[5]  M.J. Avedillo,et al.  Design of residue generators using threshold logic , 2003, 2003 46th Midwest Symposium on Circuits and Systems.

[6]  H. Garner The residue number system , 1959, IRE-AIEE-ACM '59 (Western).

[7]  Laurent Imbert,et al.  a full RNS implementation of RSA , 2004, IEEE Transactions on Computers.

[8]  Richard I. Tanaka,et al.  Residue arithmetic and its applications to computer technology , 1967 .

[9]  Vincenzo Piuri,et al.  Residue arithmetic for a fault-tolerant multiplier: the choice of the best tripe of bases , 1987 .

[10]  Victor Varshavsky,et al.  beta-Driven Threshold Elements. , 1998 .

[11]  S. J. Piestrak Self-testing checkers for arithmetic codes with any check base A , 1991, [1991] Proceedings Pacific Rim International Symposium on Fault Tolerant Systems.

[12]  P. Mohan New reverse converters for the moduli set {2n-3,2n-1,2n+1,2n+3} , 2008 .

[13]  Michael A. Soderstrand,et al.  Residue number system arithmetic: modern applications in digital signal processing , 1986 .

[14]  F. Petry,et al.  The digit parallel method for fast RNS to weighted number system conversion for specific moduli (2/sup k/-1,2/sup k/,2/sup k/+1) , 1997 .

[15]  Victor Varshavsky /spl beta/-driven threshold elements , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[16]  A. Lloris,et al.  A RNS-based matrix-vector-multiply FCT architecture for DCT computation , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[17]  Ricardo Chaves,et al.  {2/sup n/ + 1, 2/sup n+k/, 2/sup n/ - 1} : a new RNS moduli set extension , 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..

[18]  Reto Zimmermann,et al.  Efficient VLSI implementation of modulo (2/sup n//spl plusmn/1) addition and multiplication , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).