Variability-Tolerant Binary Content Addressable Memory Cells

Within-chip variability has become a serious problem in modern nano-scale technologies, which is particular true for semiconductor memory designs. This paper proposes fourtypes of variability-tolerant (VT) binary content addressable memory (BCAM) cells. The VT-BCAM cells are designed by separating the read port from the write port such that the sizing for read static noise margin (SNM) and write trip voltage (WTV) is decoupled. By reusing the comparison logic of a BCAM cell as the read port, moreover, only an additional transistor and a read wordline are needed. Experimental results show that in comparison with the typical BCAM cell the proposed variability-tolerant BCAM cells can provide about 0.655V increment of read SNM by paying about 13% additional cell area.

[1]  A.P. Chandrakasan,et al.  A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy , 2008, IEEE Journal of Solid-State Circuits.

[2]  A. Chandrakasan,et al.  Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[3]  Anna W. Topol,et al.  Stable SRAM cell design for the 32 nm node and beyond , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[4]  S. Kosonocky,et al.  A transregional CMOS SRAM with single, logic V/sub DD/ and dynamic power rails , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[5]  J. Lohstroh,et al.  Worst-case static noise margin criteria for logic circuits and their mathematical equivalence , 1983, IEEE Journal of Solid-State Circuits.

[6]  W. Dehaene,et al.  Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.

[7]  M. Yabuuchi,et al.  A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues , 2008, IEEE Journal of Solid-State Circuits.

[8]  J. Meindl,et al.  The impact of intrinsic device fluctuations on CMOS SRAM cell stability , 2001, IEEE J. Solid State Circuits.

[9]  N. Vallepalli,et al.  A 3-GHz 70MB SRAM in 65nm CMOS technology with integrated column-based dynamic power supply , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[10]  Leland Chang,et al.  A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.

[11]  Cheng-Wen Wu,et al.  A Low-Power CAM Design for LZ Data Compression , 2000, IEEE Trans. Computers.

[12]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[13]  R.H. Dennard,et al.  An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches , 2008, IEEE Journal of Solid-State Circuits.