Compensating the overlay modeling errors in lithography process of wafer stepper

The overlay modeling errors are commonly modeled as the sum of inter-field and intra-field errors in lithography process of wafer stepper. The inter-field errors characterize the global effect while the intra-field errors represent the local effect. To have a better resolution and alignment accuracy, it is important to model the overlay errors and compensate them into tolerances. This paper proposes a weighted least squares (WLS) estimator for two general overlay error models such that more accurate linear term parameters of the overlay error can be obtained. First, the least squares (LS) estimator is applied to obtain the parameters of linear and nonlinear terms. We intend to estimate the parameters of linear term while taking the nonlinear term as our modeling residual errors. Next, we use the WLS estimator to obtain more accurate parameters of linear term and thus reduced the modeling errors by choosing appropriate stepper control parameters. The WLS estimator is applied to a real data set collecting 537 wafers from a wafer fabrication facility. The test results demonstrate that the estimated linear term parameters of the WLS estimator are much more close to the assumed ones than the LS estimator.

[1]  Chen-Fu Chien,et al.  MODELING OVERLAY ERRORS AND SAMPLING STRATEGIES TO IMPROVE YIELD , 2001 .

[2]  Zone-Ching Lin,et al.  Multiple linear regression analysis of the overlay accuracy model , 1999, ICMTS 1999.

[3]  J. Morris,et al.  Monitoring process manufacturing performance , 2002 .

[4]  Mansfield Merriman A text book on the method of least squares , 1897 .

[5]  D.S. Perloff A four-point electrical measurement technique for characterizing mask superposition errors on semiconductor wafers , 1978, IEEE Journal of Solid-State Circuits.

[6]  Don MacMillen,et al.  Analysis Of Image Field Placement Deviations Of A 5x Microlithographic Reduction Lens , 1982, Advanced Lithography.

[7]  S. Joe Qin,et al.  Variance component analysis based fault diagnosis of multi-layer overlay lithography processes , 2009 .

[8]  Zone-Ching Lin,et al.  A study of improving overlay accuracy for a stepper in IC manufacture , 1998 .

[9]  John R. Wolberg,et al.  Data Analysis Using the Method of Least Squares: Extracting the Most Information from Experiments , 2005 .

[10]  Kwang-Hyun Cho,et al.  Run-to-run overlay control of steppers in semiconductor manufacturing systems based on history data analysis and neural network modeling , 2005 .

[11]  Kwang-Hyun Cho,et al.  Run-to-run overlay control of steppers in semiconductor manufacturing systems based on history data analysis and neural network modeling , 2005, IEEE Transactions on Semiconductor Manufacturing.

[12]  Chen-Fu Chien,et al.  Design of a sampling strategy for measuring and compensating for overlay errors in semiconductor manufacturing , 2003 .

[13]  Ryuhei Miyashiro,et al.  Optimization of alignment in semiconductor lithography equipment , 2009 .

[14]  Tom Batchelder Simple Metal Lift-Off Process For 1 Micron Al/5% Cu Lines , 1981, Advanced Lithography.

[15]  William H. Arnold Image Placement Differences Between 1:1 Projection Aligners And 10:1 Reduction Wafer Steppers , 1983, Advanced Lithography.

[16]  James S. Lekas,et al.  Overlay sample plan optimization for the detection of higher order contributions to misalignment , 1994 .

[17]  C. Gould Advanced process control: basic functionality requirements for lithography , 2001, 2001 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (IEEE Cat. No.01CH37160).

[18]  Chen-Fu Chien,et al.  A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing , 2006, J. Intell. Manuf..