Different Approaches for Clock Skew Analysis in Present and Future Synchronous IC's

One of the major performance limitations in chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Clock skew can limit overall circuit performance, or even cause functional errors. The main goal of this paper is to analyse and compare the most popular analytical models for estimating the clock skew for present and future VLSI systems. These models are compared for a generic global clock distribution network (an H-tree) with a JAVA program. Finally based on the presented models, a prevision for the clock skew value in upcoming technology nodes will be given.

[1]  Xiaohong Jiang,et al.  Statistical skew modeling for general clock distribution networks in presence of process variations , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[2]  H. T. Kung,et al.  Synchronizing Large VLSI Processor Arrays , 1983, IEEE Transactions on Computers.

[3]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[4]  Yehea I. Ismail,et al.  Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[5]  James D. Meindl,et al.  System-on-a-chip global interconnect optimization , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[6]  P. Zarkesh-Ha,et al.  Characterization and modeling of clock skew with process variations , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[7]  Hermann Kopetz,et al.  Clock Synchronization in Distributed Real-Time Systems , 1987, IEEE Transactions on Computers.

[8]  Resve A. Saleh,et al.  Clock skew verification in the presence of IR-drop in the powerdistribution network , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  H. T. Kung,et al.  Synchronizing Large VLSI Processor Arrays , 1985, IEEE Trans. Computers.

[10]  Eby G. Friedman.  Clock distribution networks in VLSI circuits and systems , 1995 .

[11]  S.J. Fang,et al.  Control of dielectric chemical mechanical polishing (CMP) using an interferometry based endpoint sensor , 1998, Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).

[12]  Steven D. Kugelmass,et al.  A probabilistic model for clock skew , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[13]  R. Allmon,et al.  High-performance microprocessor design , 1998, IEEE J. Solid State Circuits.

[14]  James D. Meindl,et al.  An optimal partition between on-chip and on-board interconnects , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[15]  M. Hatamian,et al.  Parallel bit-level pipelined VLSI designs for high-speed signal processing , 1987, Proceedings of the IEEE.