Efficient testing methodologies for conditional sum adders

This paper presents efficient testing methodologies for conditional sum adders. A conditional sum adder consists of conditional cells and selection cells. We propose a design-for-testability (DFT) technique to modify the conditional cells of a conditional sum adder. Then a test scheme is used for detecting the conditional sum adder with single cell fault model (CFM). The proposed test scheme only needs very low-test complexity to test a conditional sum adder. For example, the number of test patterns for a 64-bit conditional sum adder is only 9. The ratio of the number of test patterns of the proposed test scheme to the number of the test patterns of the previous scheme (Becker et al., 1995) is only about 1%. Also, experimental results show that the area overhead is only about 2.8% for a 64-bit conditional sum adder with the DFT scheme.

[1]  Jin-Fu Li,et al.  Efficient FFT network testing and diagnosis schemes , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[2]  John P. Hayes,et al.  On the design of fast, easily testable ALU's , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Janak H. Patel,et al.  A Minimum Test Set for Multiple Fault Detection in Ripple Carry Adders , 1987, IEEE Transactions on Computers.

[4]  Peter R. Cappello,et al.  Easily Testable Iterative Logic Arrays , 1990, IEEE Trans. Computers.

[5]  Bernd Becker.  Efficient Testing of Optimal Time Adders , 1988, IEEE Trans. Computers.

[6]  Jien-Chung Lo,et al.  A Fast Binary Adder with Conditional Carry Generation , 1997, IEEE Trans. Computers.

[7]  Nai-Wei Lo,et al.  Fault Tolerant Algorithms for Broadcasting on the Star Graph Network , 1997, IEEE Trans. Computers.

[8]  Shyue-Kung Lu,et al.  Easily testable and fault-tolerant FFT butterfly networks , 2000 .

[9]  Chin-Long Wey,et al.  Test generation of C-testable array dividers , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[10]  John P. Hayes,et al.  Testability of Convergent Tree Circuits , 1996, IEEE Trans. Computers.

[11]  Shyue-Kung Lu,et al.  C-testable design techniques for iterative logic arrays , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Tsutomu Sasao,et al.  On the adders with minimum tests , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

[13]  Rolf Drechsler,et al.  On the generation of area-time optimal testable adders , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..