A New HLS Allocation Algorithm for Efficient DSP Utilization in FPGAs

In this paper, an algorithm of allocation for FPGA dedicated HLS flow is proposed. This algorithm takes as input a Data Flow Graph (DFG) and provides an optimized implementation of the considered DFG. The proposed approach allows an efficient resource utilization thanks to series of tests and processes done on the DFG’s nodes. We compare our method considering different design goals against several implementation techniques. The results show an enhancement in terms of LUT utilization reaching up to 89%. The power consumption has also been improved by up to 37%. Finally the maximum frequency increased significantly thanks to the efficient use of FPGA DSP blocks.

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