A test optimized dynamic reconfigurable CPLD for structured ASIC technology

This paper presents testability optimizations for a dynamic reconfigurable CPLD (Complex Programmable Logic Device) architecture for structured ASIC technology. A CPLD architecture controlled by on chip memory can be built on structured ASIC technology to eliminate the drawback of fixed wire routing. In this paper we analyze the test coverage loss due to use of memory bits to control the logic functions and propose solutions to regain the coverage with no area and timing penalty. When compared to other synthesizable programmable cores ideas, our implementation show test coverage improvement with no area increase and performance degradation.