Multilevel reverse-carry computation for comparison and for sign and overflow detection in addition

A fast calculation of the most-significant carry in an addition is required in several applications, such as comparisons of two operands by performing their difference, sign detection, and overflow detection. It has been proposed to calculate this carry by detecting the most-significant carry chain and collecting the carry after this chain. The detection can be implemented by a prefix tree of AND gates and the collecting by a multi-input OR or by a connection with tristate buffers. We have performed an estimate of the delay of this implementation for a datapath width of 64 bits and conclude that it is not significantly faster than the traditional carry-lookahead based method. We propose a multilevel implementation, which allows the overlap of successive levels thereby reducing the overall delay. For 64-bit operands we estimate a delay reduction of about 15% with respect to the traditional carry-lookahead based method, with a similar number of gates and number and length of interconnections.

[1]  Michael J. Flynn,et al.  The SNAP project: design of floating point arithmetic units , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

[2]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[3]  M. Ercegovac,et al.  Division and Square Root: Digit-Recurrence Algorithms and Implementations , 1994 .

[4]  M.D. Ercegovac,et al.  Sign detection and comparison networks with a small number of transitions , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[5]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[6]  W. Paul,et al.  Computer Architecture , 2000, Springer Berlin Heidelberg.

[7]  D. N. Jayasimha,et al.  The half-adder form and early branch condition resolution , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.

[8]  Peter-Michael Seidel,et al.  How many logic levels does floating-point addition require? , 1998, Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273).

[9]  Simon Knowles,et al.  A family of adders , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).