A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs

Resistive defects in FinFET SRAMs are an important challenge for manufacturing test in submicron technologies, as they may cause dynamic faults, which are hard to detect and therefore may increase the number of test escapes. This paper presents a defect-oriented test that uses On-Chip Current Sensors (OCCSs) to detect weak resistive defects by monitoring the current consumption of FinFET SRAM cells. Using OCCSs, all resistive defects injected in single cells considered in this paper have been detected within a certain accuracy by applying 5 read or write operations only, independent whether they cause static or dynamic faults. The proposed approach has been validated and the detection accuracy has been evaluated. Simulation results show that the approach is even able to detect weak resistive defects that do not sensitize faults at the functional level, thus able to increase the reliability of devices.

[1]  Fabian Vargas,et al.  Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations , 2016, Microelectron. Reliab..

[2]  Arnaud Virazel,et al.  Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test , 2005, J. Electron. Test..

[3]  Yervant Zorian,et al.  Memory Physical Aware Multi-Level Fault Diagnosis Flow , 2018, IEEE Transactions on Emerging Topics in Computing.

[4]  Fabian Vargas,et al.  Technique based on On-Chip Current Sensors and Neighbourhood Comparison Logic to detect resistive-open defects in SRAMs , 2013, 2013 14th Latin American Test Workshop - LATW.

[5]  Jean-Pierre Colinge,et al.  FinFETs and Other Multi-Gate Transistors , 2007 .

[6]  Niraj K. Jha,et al.  Introduction to Nanotechnology , 2011 .

[7]  Akhil Garg,et al.  Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time , 2010, J. Electron. Test..

[8]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[9]  Arnaud Virazel,et al.  Resistive-open defects in embedded-SRAM core cells: analysis and march test solution , 2004, 13th Asian Test Symposium.

[10]  D. M. H. Walker,et al.  IDDX-based test methods: A survey , 2004, TODE.

[11]  J. Bokor,et al.  FinFET-a quasi-planar double-gate MOSFET , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[12]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[13]  K. J. Kuhn,et al.  Considerations for Ultimate CMOS Scaling , 2012, IEEE Transactions on Electron Devices.

[14]  Chen-Wei Lin,et al.  Investigation of gate oxide short in FinFETs and the test methods for FinFET SRAMs , 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

[15]  C. Hora,et al.  IDDQ-based diagnosis at very low voltage (VLV) for bridging defects , 2007 .

[16]  Said Hamdioui,et al.  Testing static and dynamic faults in random access memories , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[17]  Daniel Arbet,et al.  A new IDDT test approach and its efficiency in covering resistive opens in SRAM arrays , 2014, Microprocess. Microsystems.

[18]  Jen-Chieh Yeh,et al.  A Systematic Approach to Memory Test Time Reduction , 2008, IEEE Design & Test of Computers.

[19]  Giorgio Di Natale,et al.  March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs , 2007, IET Comput. Digit. Tech..

[20]  Arnaud Virazel,et al.  Advanced test methods for SRAMs , 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

[21]  Alfredo Benso,et al.  March AB, March AB1: new March tests for unlinked dynamic memory faults , 2005, IEEE International Conference on Test, 2005..

[22]  S SabadeSagar,et al.  IDDX-based test methods , 2004 .

[23]  Yervant Zorian,et al.  Fault modeling and test algorithm creation strategy for FinFET-based memories , 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

[24]  Niraj K. Jha,et al.  Nanoelectronic circuit design , 2011 .

[25]  Niraj K. Jha,et al.  FinFETs: From Devices to Architectures , 2014 .

[26]  D. Hisamoto,et al.  A fully depleted lean-channel transistor (DELTA)-a novel vertical ultra thin SOI MOSFET , 1989, International Technical Digest on Electron Devices Meeting.

[27]  Tiago R. Balen,et al.  Analyzing the behavior of FinFET SRAMs with resistive defects , 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[28]  Isabelle Ferain,et al.  Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors , 2011, Nature.

[29]  Arnaud Virazel,et al.  Basics on SRAM Testing , 2010 .