Charge Pump Architectures Based on Dynamic Gate Control of the Pass-Transistors
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[1] M. Pasotti,et al. Power efficient charge pump in deep submicron standard CMOS technology , 2003, Proceedings of the 27th European Solid-State Circuits Conference.
[2] L. Colalongo,et al. A new integrated charge pump architecture using dynamic biasing of pass transistors , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..
[3] G. Palumbo,et al. Charge-pump circuits: power-consumption optimization , 2002 .
[4] Y. J. Park,et al. A new charge pump without degradation in threshold voltage due to body effect [memory applications] , 2000, IEEE Journal of Solid-State Circuits.
[5] John F. Dickson,et al. On-Chip High-Voltage Generation in Integrated Circuits Using an Improved Multiplier Technique , 1976 .
[6] Luigi Colalongo,et al. A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[7] Chia-Hung Wei,et al. A CMOS charge pump for sub-2.0 V operation , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[8] Ming-Dou Ker,et al. Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes , 2006, IEEE J. Solid State Circuits.
[9] Jieh-Tsorng Wu,et al. Low Supply Voltage CMOS Charge Pumps , 1997 .