The MOSART Mapping Optimization for Multi-Core ARchiTectures

MOSART project addresses two main challenges of prevailing architectures: (1) The global interconnect and memory bottleneck due to a single, globally shared memory with high access times and power consumption; (2) The difficulties in programming heterogeneous, multi-core platforms MOSART aims to overcome these through a multi-core architecture with distributed memory organization, a Network-on-Chip (NoC) communication backbone and configurable processing cores that are scaled, optimized and customized together to achieve diverse energy, performance, cost and size requirements of different classes of applications. MOSART achieves this by: (1) Providing platform support for management of abstract data structures including middleware services and a run-time data manager for NoC based communication infrastructure; (2) Developing tool support for parallelizing and mapping applications on the multi-core target platform and customizing the processing cores for the application.

[1]  Jari Kreku,et al.  Workload simulation method for evaluation of application feasibility in a mobile multiprocessor platform , 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..

[2]  Francky Catthoor,et al.  Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information , 2008, 2008 Asia and South Pacific Design Automation Conference.

[3]  Paul R. Wilson,et al.  Dynamic Storage Allocation: A Survey and Critical Review , 1995, IWMM.

[4]  Francky Catthoor,et al.  Software metadata: Systematic characterization of the memory behaviour of dynamic applications , 2010, J. Syst. Softw..

[5]  Geert Vanmeerbeeck,et al.  Automatic workload generation for system-level exploration based on modified GCC compiler , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[6]  Yang Qu,et al.  Combining UML2 Application and SystemC Platform Modelling for Performance Evaluation of Real-Time Embedded Systems , 2008, EURASIP J. Embed. Syst..

[7]  Shuming Chen,et al.  Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[8]  Thomas J. Ashby,et al.  MPA: Parallelizing an Application onto a Multicore Platform Made Easy , 2009, IEEE Micro.

[9]  Jean-Michel Chabloz,et al.  A flexible communication scheme for rationally-related clock frequencies , 2009, 2009 IEEE International Conference on Computer Design.