ASICs for a High Performance IVIulti Processor Systemfor Photo-realistic Image Synthesis

A number of ASIC architectures are presented to build a system for fast photorealistic rendering of complex images. Both ray tracing and radiosity algorithms can be used. The system consists of a number of custom and general purpose processors that communicate through a serial interface. The scene database is split into three disjoint data sets. Rays are passed between processors. The load is dynamically balanced by means of a load balancing processor. Fine grain and coarse grain parallelism are exploited.

[1]  Bengt-Olaf Schneider,et al.  Ray Tracing Rational B-Spline Patches in VLSI , 1988, Advances in Computer Graphics Hardware.

[2]  John A. Kapenga,et al.  VLSI Chip for Ray Tracing Bicubic Patches , 1987, Advances in Computer Graphics Hardware.

[3]  Kadi Bouatouch,et al.  A VLSI Chip for Ray Tracing Bicubic Patches , 1989, Eurographics.

[4]  Brian Wyvill,et al.  Multiprocessor Ray Tracing , 1986, Comput. Graph. Forum.

[5]  John A. Kapenga,et al.  The Feasibility of a VLSI Chip for Ray Tracing Bicublic Patches , 1987, IEEE Computer Graphics and Applications.