Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique

In this work, we implement a computational statistics technique for design optimization of integrated circuits (ICs). Integration of a well-known circuit simulation software and central composite design method enables us to construct a second-order response surface model (RSM) for each concerned constraint. After construction of RSMs, we verify the adequacy and accuracy using the normal residual plots and their residual of squares. The constructed models are further employed for design optimization of current mirror amplifier ICs with 0.18@mm CMOS devices. By considering the voltage gain, cut-off frequency, phase margin, common-mode rejection ratio and slew-rate, six designing parameters including the width and length of different transistors are selected and optimized to fit the targets.

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