Design techniques and test methodology for low-power TCAMs

Ternary content addressable memories (TCAMs) are gaining importance in high-speed lookup-intensive applications. However, the high cost and power consumption are limiting their popularity and versatility. TCAM testing is also time consuming due to the complex integration of logic and memory. In this paper, we present a comprehensive review of the design techniques for low-power TCAMs. We also propose a novel test methodology for various TCAM components. The proposed test algorithms show significant improvement over the existing algorithms both in test complexity and fault coverage

[1]  Manoj Sachdev,et al.  Transistor-level fault analysis and test algorithm development for ternary dynamic content addressable memories , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[2]  N. Mohan,et al.  A static power reduction technique for ternary content addressable memories , 2004, Canadian Conference on Electrical and Computer Engineering 2004 (IEEE Cat. No.04CH37513).

[3]  Frans P. M. Beenker,et al.  Fault modeling and test algorithm development for static random access memories , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[4]  Jin-Fu Li,et al.  Testing and Diagnosis Methodologies for Embedded Content Addressable Memories , 2003, J. Electron. Test..

[5]  K. Pagiamtzis,et al.  Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[6]  Chung-Hsun Huang,et al.  Design of high-performance CMOS priority encoders and incrementer/decrementers using multilevel lookahead and multilevel folding techniques , 2002 .

[7]  Jin-Fu Li,et al.  Testing priority address encoder faults of content addressable memories , 2005, IEEE International Conference on Test, 2005..

[8]  Cheol Kim,et al.  Modeling and Testing of Faults in TCAMs , 2004, AsiaSim.

[9]  H. Bergh,et al.  A fault-tolerant associative memory with high-speed operation , 1990 .

[10]  K. Fujishima,et al.  A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture , 2005, IEEE Journal of Solid-State Circuits.

[11]  Jin-Fu Li,et al.  March-based RAM diagnosis algorithms for stuck-at and coupling faults , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[12]  Michael John Sebastian Smith,et al.  Application-specific integrated circuits , 1997 .

[13]  C. A. Zukowski,et al.  Use of selective precharge for low-power on the match lines of content-addressable memories , 1997, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. NO.97TB100159).

[14]  Jin-Fu Li,et al.  Modeling and testing comparison faults for ternary content addressable memories , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[15]  Piotr R. Sidorowicz.  Modeling and testing transistor faults in content-addressable memories , 1999, Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing.

[16]  Ali Sheikholeslami,et al.  A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme , 2003, IEEE J. Solid State Circuits.

[17]  A. Roth,et al.  Advanced ternary CAM circuits on 0.13 /spl mu/m logic process technology , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[18]  H. Hara,et al.  A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies , 1996 .

[19]  Ali Sheikholeslami,et al.  A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories , 2003 .

[20]  José G. Delgado-Frias,et al.  A VLSI high-performance encoder with priority lookahead , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[21]  G. Kasai,et al.  200MHz/200MSPS 3.2W at 1.5V Vdd, 9.4Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[22]  Manoj Sachdev,et al.  Low power dual matchline ternary content addressable memory , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).