Sequential engineering change order under retiming and resynthesis
暂无分享,去创建一个
[1] Po-Kai Huang,et al. Interpolation-based incremental ECO synthesis for multi-error logic rectification , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).
[2] Shi-Yu Huang,et al. Error correction based on verification techniques , 1996, 33rd Design Automation Conference Proceedings, 1996.
[3] Jarrod A. Roy,et al. ECO-system: Embracing the Change in Placement , 2007 .
[4] Narendra V. Shenoy,et al. Efficient Implementation Of Retiming , 1994, IEEE/ACM International Conference on Computer-Aided Design.
[5] Joachim Keinert,et al. Intuitive ECO synthesis for high performance circuits , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[6] Jie-Hong Roland Jiang,et al. A robust functional ECO engine by SAT proof minimization and interpolation techniques , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[7] Jie-Hong Roland Jiang,et al. TRECO: Dynamic technology remapping for timing Engineering Change Orders , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[8] Charles E. Leiserson,et al. Retiming synchronous circuitry , 1988, Algorithmica.
[9] Karem A. Sakallah,et al. REVERSE: Efficient Sequential Verification for Retiming , 2003 .
[10] Philippe Coussy,et al. High-Level Synthesis: from Algorithm to Digital Circuit , 2008 .
[11] Giovanni De Micheli. Synchronous logic synthesis: algorithms for cycle-time minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[12] Robert K. Brayton,et al. Recording Synthesis History for Sequential Verification , 2008, 2008 Formal Methods in Computer-Aided Design.
[13] William Craig,et al. Linear reasoning. A new form of the Herbrand-Gentzen theorem , 1957, Journal of Symbolic Logic.
[14] Ruchir Puri,et al. DeltaSyn: An efficient logic difference optimizer for ECO synthesis , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.
[15] Martin D. F. Wong,et al. An ECO routing algorithm for eliminating coupling-capacitance violations , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[16] Yao-Wen Chang,et al. Redundant-wires-aware ECO timing and mask cost optimization , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[17] Robert K. Brayton,et al. Retiming and resynthesis: optimizing sequential networks with combinational techniques , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[18] Robert K. Brayton,et al. Retiming and Resynthesis: A Complexity Perspective , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[19] Iris Hui-Ru Jiang,et al. Matching-based minimum-cost spare cell selection for design changes , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[20] Robert K. Brayton,et al. Fast Minimum-Register Retiming via Binary Maximum-Flow , 2007 .
[21] Jie-Hong Roland Jiang,et al. Inductive equivalence checking under retiming and resynthesis , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.
[22] Ibrahim N. Hajj,et al. Design error diagnosis and correction via test vector simulation , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[23] M. Marek-Sadowska,et al. Logic synthesis for engineering change , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Chun-Nan Chou,et al. Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[25] Robert K. Brayton,et al. Scalable min-register retiming under timing and initializability constraints , 2008, 2008 45th ACM/IEEE Design Automation Conference.
[26] Jason Cong,et al. An implicit connection graph maze routing algorithm for ECO routing , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).
[27] Yao-Wen Chang,et al. Simultaneous functional and timing ECO , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).