High performance processor array for image processing

The ASIC implementation of a digital cellular visual microprocessor architecture is introduced. The processor array is constructed of simple, locally interconnected 8 bit microprocessors, operating in an extended SIMD mode. The processor array can be equipped with on-chip photo diode array, using 3D integration technology

[1]  Tamás Roska,et al.  Digital implementation of cellular sensor-computers , 2006, Int. J. Circuit Theory Appl..

[2]  S. Espejo,et al.  A CNN universal chip in CMOS technology , 1994, Proceedings of the Third IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA-94).

[3]  Kiyoharu Aizawa,et al.  A computational image sensor with adaptive pixel-based integration time , 2001 .

[4]  Tamás Roska.  Computer-Sensors: Spatial-Temporal Computers for Analog Array Signals, Dynamically Integrated with Sensors , 1999, J. VLSI Signal Process..

[5]  Ari Paasio,et al.  A 176 x 144 processor binary I/O CNN-UM chip design , 1999 .

[6]  Tamás Roska,et al.  The CNN universal machine: an analogic array computer , 1993 .

[7]  Ángel Rodríguez-Vázquez,et al.  ACE16k: A Programmable Focal Plane Vision Processor with 128 x 128 Resolution , 2001 .

[8]  Piotr Dudek,et al.  A general-purpose processor-per-pixel analog SIMD vision chip , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[9]  A. Dawidziuk,et al.  Minimum size 0.5 micron CMOS programmable 48 by 48 CNN test chip , 1997 .

[10]  S. Espejo,et al.  Universal Chip in Cmos Technology 1 , 1996 .

[11]  A. Rodriguez-Vazquez,et al.  A 64/spl times/64 CNN universal chip with analog and digital I/O , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[12]  Ángel Rodríguez-Vázquez,et al.  A CNN UNIVERSAL CHIP IN CMOS TECHNOLOGY , 1996 .