An algorithm for simulating power/ground networks using Pade approximants and its symbolic implementation

This paper presents an event-driven algorithm and its symbolic implementation for the analysis of power and ground (P/G) bus networks. The algorithm uses frequency-domain techniques and moment matching approaches based on Pade approximants to estimate the transfer function at each node in the P/G network. Afterwards, the transient waveforms are extracted for each node. The process requires repetitive simulation of a linear and time-variant (from one time event to the next) circuit model for the P/G network which is the reason a symbolic implementation was produced. The P/G network is modeled by a hierarchical combination of mesh and tree structures that are composed of a collection of RC-/spl pi/-segments and pulldown (or pullup) switches. The switches are symbolically represented by Boolean variables and a compiled symbolic code is generated only once for each P/G network. The transient waveforms are then produced by repetitive evaluation of the symbolic output. The results show that the symbolic implementation is an order of magnitude faster, with reasonably good accuracy, than using a traditional analog circuit simulator like SPICE.

[1]  Georges Gielen,et al.  ISAAC: a symbolic simulator for analog integrated circuits , 1989 .

[2]  Sung-Mo Kang,et al.  Fast Approximation of the Transient Response of Lossy Transmission Line Trees , 1993, 30th ACM/IEEE Design Automation Conference.

[3]  M. M. Hassoun,et al.  A hierarchical network approach to symbolic analysis of large-scale networks , 1995 .

[4]  J.L. Huertas,et al.  An advanced symbolic analyzer for the automatic generation of analog circuit design equations , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

[5]  Baher Haroun,et al.  Power estimation tool for sub-micron CMOS VLSI circuits , 1992, ICCAD.

[6]  Wolfgang Fichtner,et al.  Lazy-expansion symbolic expression approximation in SYNAP , 1992, ICCAD.

[7]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  J. Starzyk,et al.  Flowgraph analysis of large electronic networks , 1986 .

[9]  Ulrich Jagau.  SIMCURRENT-an efficient program for the estimation of the current flow of complex CMOS circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[10]  Qicheng Yu,et al.  Efficient approximation of symbolic network functions using matroid intersection algorithms , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[11]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluator , 1991, 28th ACM/IEEE Design Automation Conference.

[12]  L. Spaanenburg,et al.  PROCEEDINGS OF THE IEEE 1995 CUSTOM INTEGRATED CIRCUITS CONFERENCE , 1995 .

[13]  Stefano Manetti,et al.  A new symbolic program package for the interactive design of analog circuits , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[14]  H. B. Bakoglu,et al.  Circuits, interconnections, and packaging for VLSI , 1990 .

[15]  A. Nabavi-Lishi,et al.  Delay and bus current evaluation in CMOS logic circuits , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.

[16]  Ibrahim N. Hajj,et al.  Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Mark Horowitz,et al.  Techniques for calculating currents and voltages in VLSI power supply networks , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  P. M. Lin,et al.  SNAP: A computer program for generating symbolic network functions , 1970 .

[19]  Carl Sechen,et al.  Accurate extraction of simplified symbolic pole/zero expressions for large analog IC's , 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

[20]  Akhilesh Tyagi.  Hercules: A Power Analyzer for MOS VLSI Circuits , 1987 .

[21]  S.-M. Chang,et al.  Matrix reduction and numerical approximation during computation techniques for symbolic analog circuit analysis , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[22]  S. Chowdhury,et al.  Estimation of maximum currents in MOS IC logic circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Nicholas C. Rumin,et al.  Delay and bus current evaluation in CMOS logic circuits , 1992, ICCAD.

[24]  Ralf Sommer,et al.  More efficient algorithms for symbolic network analysis: supernodes and reduced loop analysis , 1993 .

[25]  M. Hassoun,et al.  Symbolic analysis of large-scale networks using a hierarchical signal flowgraph approach , 1993 .

[26]  P. Wambacq,et al.  A family of matroid intersection algorithms for the computation of approximated symbolic network functions , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[27]  Sung-Mo Kang,et al.  Physical Design for Multichip Modules , 1994 .

[28]  Michel Nakhla,et al.  Asymptotic waveform Evaluation , 1994 .

[29]  M. M. Alaybeyi,et al.  AWE-Inspired , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[30]  Rob A. Rutenbar,et al.  Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis , 1994, IEEE J. Solid State Circuits.

[31]  Rob A. Rutenbar,et al.  Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization , 1995 .

[32]  Ibrahim N. Hajj,et al.  Probabilistic simulation for reliability analysis of CMOS VLSI circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[33]  A. TUSTIN,et al.  Automatic Control Systems , 1950, Nature.