Low Power 1-Bit 9T Full Adder Cell using XNOR Logic

In this paper a new low power and high performance 9T adder circuit using XNOR gate architecture is proposed which improves the performance of existing 8T adder by sacrificing the MOS transistor count by one. Simulation results demonstrate the superiority of the proposed adder against existing 8T adder in terms of power consumption and temperature sustainability. The combination of low power and better temperature sustainability makes the proposed full adder an optimal option for low power and energy efficient design. All simulations are performed on 90nm standard model on Tanner EDA tool version 13.0. Keywords—8T, 9T, XNOR gate, full adder and low power.