Scaled Quantum Circuits Emulated with Room Temperature p-Bits

Exploiting a well-established mapping from a d-dimensional quantum Hamiltonian to a d+1-dimensional classical Hamiltonian that is commonly used in software quantum Monte Carlo algorithms, we propose a scalable hardware emulator where quantum circuits are emulated with room temperature p-bits. The proposed emulator operates with probabilistic bits (p-bit) that fluctuate between logic 0 and 1, that are suitably interconnected with a crossbar of resistors or conventional CMOS devices. One particularly compact hardware implementation of a p-bit is based on the standard 1 transistor/1 Magnetic Tunnel Junction (1T/1MTJ) cell of the emerging Embedded Magnetoresistive RAM (eMRAM) technology, with a simple modification: The free layer of the MTJ uses a thermally unstable nanomagnet so that the resistance of the MTJ fluctuates in the presence of thermal noise. Using established device models for such p-bits and interconnects simulated in SPICE, we demonstrate a faithful mapping of the Transverse Ising Hamiltonian to its classical counterpart, by comparing exact calculations of averages and correlations. Even though we focus on the Transverse Ising Hamiltonian, many other "stoquastic" Hamiltonians - avoiding the sign problem - can be mapped to the hardware emulator. For such systems, large scale integration of the eMRAM technology can enable the intriguing possibility of emulating a very large number of q-bits by room temperature p-bits. The compact and low-level representation of the p-bit offers the possibility of greater efficiency and scalability compared to standard software implementations of quantum Monte Carlo methods.

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