Heterogeneous Two-Level Logic and Its Density and Fault Tolerance Implications in Nanoscale Fabrics

Most proposed nanoscale computing architectures are based on a certain type of two-level logic family, e.g., AND-OR, NOR-NOR, NAND-NAND, etc. In this paper, a new fabric architecture that combines different logic families in the same nanofabric is proposed for higher density and better defect tolerance. To achieve this, we apply very minor modifications on the way of controlling nanogrids, while the basic manufacturing requirements remain the same. The fabric that is based on the new heterogeneous two-level logic yields higher density for the applications mapped to it. We find that it also improves the efficiency of fault tolerance techniques as it significantly simplifies the designs. In addition, we found that it enables voting at nanoscale that can improve fault tolerance further. A nanoscale processor is implemented for evaluation purposes. We found that compared with an implementation on a Nanoscale Application-Specific IC (NASIC) fabric with one type of two-level logic, the density of this processor improves by up to 52% by using the heterogeneous logic. Furthermore, the yield is improved by 15% at 2% defective transistors and by 147% at 5% defect rates. Detailed analysis on density and yield is provided. The approach is applicable in grid-based fabrics in general, e.g., it can be used in both NASIC and hybrid semiconductor/nanowire/molecular (CMOL) designs.

[1]  Teng Wang,et al.  CMOS Control Enabled Single-Type FET NASIC , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[2]  D. Strukov,et al.  CMOL: Devices, Circuits, and Architectures , 2006 .

[3]  Charles M. Lieber,et al.  Doping and Electrical Transport in Silicon Nanowires , 2000 .

[4]  David P. Norton,et al.  Depletion-mode ZnO nanowire field-effect transistor , 2004 .

[5]  Teng Wang,et al.  Latching on the wire and pipelining in nanoscale designs , 2004 .

[6]  Teng Wang,et al.  Opportunities and challenges in application-tuned circuits and architectures based on nanodevices , 2004, CF '04.

[7]  Teng Wang,et al.  Fault-Tolerant Nanoscale Processors on Semiconductor Nanowire Grids , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Wei Lu,et al.  Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures , 2004, Nature.

[9]  M. Meyyappan,et al.  Single Crystal Nanowire Vertical Surround-Gate Field-Effect Transistor , 2004 .

[10]  Csaba Andras Moritz,et al.  Wire-Streaming Processors on 2-D Nanowire Fabrics , 2005 .

[11]  Csaba Andras Moritz,et al.  Combining Circuit Level and System Level Techniques for Defect-Tolerant Nanoscale Architectures , 2006 .

[12]  Charles M. Lieber,et al.  Directed assembly of one-dimensional nanostructures into functional networks. , 2001, Science.

[13]  Tohru Yamamoto,et al.  Two-dimensional molecular electronics circuits. , 2002, Chemphyschem : a European journal of chemical physics and physical chemistry.

[14]  Dongmok Whang,et al.  Large-scale hierarchical organization of nanowire arrays for integrated nanosystems , 2003 .

[15]  K.K. Likharev,et al.  A Defect-Tolerant Architecture for Nanoelectronic Resistive Memories , 2006, 2006 7th Annual Non-Volatile Memory Technology Symposium.

[16]  C. Moritz,et al.  Towards Defect-Tolerant Nanoscale Architectures , 2006, 2006 Sixth IEEE Conference on Nanotechnology.

[17]  Robert E. Lyons,et al.  The Use of Triple-Modular Redundancy to Improve Computer Reliability , 1962, IBM J. Res. Dev..

[18]  Wei Lu,et al.  TOPICAL REVIEW: Semiconductor nanowires , 2006 .

[19]  K. Richter,et al.  Introducing Molecular Electronics , 2005 .

[20]  Charles M. Lieber,et al.  Growth and transport properties of complementary germanium nanowire field-effect transistors , 2004 .

[21]  Deug-Woo Lee,et al.  Behavior characteristics of nano-stage according to hinge structure. , 2007 .

[22]  André DeHon,et al.  Nanowire-based programmable architectures , 2005, JETC.

[23]  Charles M Lieber,et al.  Semiconductor nanowires , 2006 .

[24]  T. Cao,et al.  Logic Gates and Computation from Assembled Nanowire Building Blocks , 2001 .