Reduced Miller Capacitance in U-Shaped Channel Tunneling FET by Introducing Heterogeneous Gate Dielectric

In this letter, a novel U-shaped channel tunneling FET (UTFET) with heterogeneous gate dielectric (HG-UTFET) is designed to reduce the Miller capacitance (<inline-formula> <tex-math notation="LaTeX">$\text{C}_{\mathrm {\mathbf {M}}}$ </tex-math></inline-formula>) and to improve the performance of TFET digital circuits. Because the HG-UTFET and UTFET have the same gate dielectric near the source region, these two devices nearly have the same on-state current. But due to the smaller gate-to-drain capacitance (<inline-formula> <tex-math notation="LaTeX">$\text{C}_{\textit {gd}}$ </tex-math></inline-formula>) caused by the low-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> gate dielectric near the drain region, the HG-UTFET has smaller <inline-formula> <tex-math notation="LaTeX">$\text{C}_{\mathrm {M}}$ </tex-math></inline-formula> compared with UTFET, which will enhance the switching performance of digital circuits. The simulation results reveal that the overshoot/undershoot and rising/falling delay of the output signal in the HG-UTFET inverter are reduced a lot compared with the UTFET inverter. Results show that the <inline-formula> <tex-math notation="LaTeX">$\text{C}_{\mathrm {M}}$ </tex-math></inline-formula> and falling delay of the HG-UTFET inverter are ~45.6% and ~30.7% less than that of the UTFET inverter, respectively. Therefore, by the application of HG-UTFET, the switching performance of inverter can be enhanced a lot.

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