An accurate analytical BiCMOS delay expression and its application to optimizing high-speed BiCMOS circuits

A scheme for optimizing the overall delay of BiCMOS driver circuits is proposed in this paper. Using this optimization scheme, it is found that the delay is minimized when the maximum collector current of the bipolar transistors is equal to the onset of high current effects. Using this assumption, an accurate BiCMOS delay expression is derived in terms of the bipolar and MOS device parameters. The critical device parameters are then identified and their influence on the circuit speed discussed. An overall circuit delay expression for optimizing BiCMOS buffers is derived and a comparison made with CMOS buffers. It is shown that BiCMOS circuits have a speed advantage of 1.7 or an area advantage of about 5 for 2- mu m feature sizes. In order to predict the future performance of BiCMOS circuits, a figure of merit is derived from the delay expression. Using the figure-of-merit expression, it is seen that future BiCMOS circuits can keep the speed advantage over CMOS circuits down to submicrometer dimensions under constant load capacitance assumption. >

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