Integrated Input/Output Interconnection and Packaging for GSI

[1]  D. Miller,et al.  Optical interconnects to silicon , 2000, IEEE Journal of Selected Topics in Quantum Electronics.

[2]  Peng Su,et al.  A study of electromigration failure in Pb-free solder joints , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..

[3]  P. Kohl,et al.  Air-channel fabrication for microelectromechanical systems via sacrificial photosensitive polycarbonates , 2003 .

[4]  M. Johnson,et al.  Flip chip reliability: comparative characterization of lead free (Sn/Ag/Cu) and 63Sn/Pb eutectic solder , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[5]  S. Pozder,et al.  Analysis of flip-chip packaging challenges on copper/low-k interconnects , 2003 .

[6]  S. Sommerfeldt,et al.  Thermal performance of an integral immersion cooled multichip module package , 1993, [1993 Proceedings] Ninth Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[7]  King-Ning Tu,et al.  Electromigration in Sn-Pb solder strips as a function of alloy composition , 2000 .

[8]  R. Viswanath Thermal Performance Challenges from Silicon to Systems , 2000 .

[9]  Nam-Trung Nguyen,et al.  Development of a peristaltic pump in printed circuit boards , 2005 .

[10]  Kenneth E. Goodson,et al.  Improved heat sinking for laser-diode arrays using microchannels in CVD diamond , 1997 .

[11]  S. Sitaraman,et al.  /spl beta/-Helix: a lithography-based compliant off-chip interconnect , 2003 .

[12]  P. Kohl,et al.  Fabrication of air-channel structures for microfluidic, microelectromechanical, and microelectronic applications , 2001 .

[13]  J.D. Meindl,et al.  Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink , 2006, IEEE Electron Device Letters.

[14]  Torsten Thelemann,et al.  Liquid cooled LTCC-substrates for high power applications , 1999 .

[15]  J. Fjelstad,et al.  Reliable and low cost wafer level packaging. Process description and qualification testing results for wide area vertical expansion (WAVE/sup TM/) package technology , 2000, Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146).

[16]  J. Tao,et al.  Electromigration characteristics of copper interconnects , 1993, IEEE Electron Device Letters.

[17]  Jun He,et al.  > Replace This Line with Your Paper Identification Number (double-click Here to Edit) < 1 Materials Impact on Interconnects Process Technology and Reliability , 2004 .

[18]  A. Naeemi,et al.  Polylithic integration of electrical and optical interconnect technologies for gigascale fiber-to-the-chip communication , 2005, IEEE Transactions on Advanced Packaging.

[19]  J.D. Meindl,et al.  Sea of polymer pillars: compliant wafer-level electrical-optical chip I/O interconnections , 2003, IEEE Photonics Technology Letters.

[20]  T K Gaylord,et al.  Design, fabrication, and performance of preferential-order volume grating waveguide couplers. , 2000, Applied optics.

[21]  A. van den Berg,et al.  Micromachining of buried micro channels in silicon , 2000, Journal of Microelectromechanical Systems.

[22]  Paul S. Ho,et al.  Packaging effects on reliability of Cu/low-k interconnects , 2003 .

[23]  James D. Meindl,et al.  Interconnect Opportunities for Gigascale Integration , 2002, IEEE Micro.

[24]  Kyung-Wook Paik,et al.  Comparison of electroplated eutectic Bi/Sn and Pb/Sn solder bumps on various UBM systems , 2000, ECTC 2000.

[25]  J. Meindl,et al.  Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration , 2004, IEEE Transactions on Electron Devices.

[26]  A. Naeemi,et al.  Impact of deep sub-ambient cooling on GSI interconnect performance , 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

[27]  Chirag Suryakant Patel Compliant Wafer Level Package (CWLP) , 2001 .

[28]  M. Schmidt Wafer-to-wafer bonding for microstructure formation , 1998, Proc. IEEE.

[29]  H.Y. Zhang,et al.  Development of liquid cooling techniques for flip chip ball grid array packages with High Heat flux dissipations , 2005, IEEE Transactions on Components and Packaging Technologies.

[30]  Sungjun Im,et al.  Integrated Microchannel Cooling for Three-Dimensional Electronic Circuit Architectures , 2005 .

[31]  D.A.B. Miller,et al.  Rationale and challenges for optical interconnects to electronic chips , 2000, Proceedings of the IEEE.

[32]  C. Beddingfield,et al.  Performance of evaporated and plated bumps on organic substrates , 1998, Twenty Third IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.98CH36205).

[33]  Chi On Chui,et al.  Integration of optical polymer pillars chip I/O interconnections with Si MSM photodetectors , 2004, IEEE Transactions on Electron Devices.

[34]  J.D. Meindl,et al.  Integrated electrical, optical, and thermal high density and compliant wafer-level chip I/O interconnections for gigascale integration , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[35]  R. Shah Laminar Flow Forced convection in ducts , 1978 .

[36]  J. Meindl,et al.  Compliant wafer level package (CWLP) with embedded air-gaps for sea of leads (SoL) interconnections , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[37]  Chih-Tang Peng,et al.  Parametric reliability analysis of no-underfill flip chip package , 2001 .

[38]  James D. Meindl,et al.  Partition length between board-level electrical and optical interconnects , 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

[39]  P. Svasta,et al.  Investigation on an integrated liquid cooling system in LTCC-multilayer , 2001, 24th International Spring Seminar on Electronics Technology. Concurrent Engineering in Electronic Packaging. ISSE 2001. Conference Proceedings (Cat. No.01EX492).

[40]  B. Dang,et al.  Sea of leads compliant I/O interconnect process integration for the ultimate enabling of chips with low-k interlayer dielectrics , 2005, IEEE Transactions on Advanced Packaging.

[41]  Ansgar Wego,et al.  A self-filling micropump based on PCB technology , 2001 .

[42]  Keith A. Bowman,et al.  Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[43]  Ray T. Chen,et al.  Fully embedded board-level guided-wave optoelectronic interconnects , 2000, Proceedings of the IEEE.

[44]  James D. Meindl,et al.  Input coupling and guided-wave distribution schemes for board-level intra-chip guided-wave optical clock distribution network using volume grating coupler technology , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[45]  H. Takara,et al.  2 Gb/s operation of an optical-clock-driven monolithically integrated GaAs D-flip-flop with metal-semiconductor-metal photodetectors for high-speed synchronous circuits , 1992, IEEE Photonics Technology Letters.

[46]  James M. Pitarresi,et al.  Reliability modeling of chip scale packages , 2000, Twenty Sixth IEEE/CPMT International Electronics Manufacturing Technology Symposium (Cat. No.00CH37146).

[47]  Je-Young Chang,et al.  Convective Performance of Package Based Single Phase Microchannel Heat Exchanger , 2005 .

[48]  T. Gaylord,et al.  Optical transmission of polymer pillars for chip I/O optical interconnections , 2004, IEEE Photonics Technology Letters.

[49]  R. L. Webb,et al.  Performance and testing of thermal interface materials , 2003, Microelectron. J..

[50]  J.D. Meindl,et al.  Sea of leads: a disruptive paradigm for a system-on-a-chip (SoC) , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[51]  J. Novitsky,et al.  FormFactor introduces an integrated process for wafer-level packaging, burn-in test, and module level assembly , 1999, Proceedings International Symposium on Advanced Packaging Materials. Processes, Properties and Interfaces (IEEE Cat. No.99TH8405).

[52]  Thomas K Gaylord,et al.  Quasi-free-space optical coupling between diffraction grating couplers fabricated on independent substrates. , 2004, Applied optics.

[53]  James D. Meindl,et al.  Interconnect Technology and Design for Gigascale Integration , 2003 .

[54]  H. Thacker,et al.  Optimal implementation of sea of leads (SoL) compliant interconnect technology , 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

[55]  Y.C. Lee,et al.  RF and mechanical characterization of flip-chip interconnects in CPW circuits with underfill , 1998, 1998 IEEE MTT-S International Microwave Symposium Digest (Cat. No.98CH36192).

[56]  K. DeHaven,et al.  Controlled collapse chip connection (C4)-an enabling technology , 1994, 1994 Proceedings. 44th Electronic Components and Technology Conference.

[57]  M. Ruzzene,et al.  Accelerated reliability - thermal and mechanical fatigue solder joints methodologies , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[58]  Qi Zhu,et al.  Design optimization of One-Turn Helix - a novel compliant off-chip interconnect , 2002, ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258).

[59]  Chao-An Lin,et al.  Numerical Investigations Of The Thermal Characteristics Of A Flip-Chip BGA Package With And Without Heat Sink , 2004 .

[60]  Chandrakant D. Patel,et al.  Design and performance evaluation of a compact thermosyphon , 2002 .

[61]  Rajen Chanchani,et al.  mini Ball Grid Array (mBGA) assembly on MCM-L boards , 1997 .

[62]  Hong Xue,et al.  Experimental study on laminar heat transfer in microchannel heat sink , 2002, ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258).

[63]  J. Black,et al.  Electromigration—A brief survey and some recent results , 1969 .

[64]  T. Kenny,et al.  Closed-loop electroosmotic microchannel cooling system for VLSI circuits , 2002 .

[65]  R. Dekker,et al.  Integrated micro-channel cooling in silicon , 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

[66]  U.A. Shrivastava,et al.  Inductance calculation and optimal pin assignment for the design of pin grid array and chip-carrier packages , 1989, Proceedings., 39th Electronic Components Conference.

[67]  Muhannad S. Bakir,et al.  Sea of leads ultra high-density compliant wafer-level packaging technology , 2002, 52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345).

[68]  M. Patterson,et al.  Stacked Microchannel Heat Sinks for Liquid Cooling of Microelectronics , 2004 .

[69]  J.D. Meindl,et al.  Sea of dual mode polymer pillar I/O interconnections for gigascale integration , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[70]  G. Wallis,et al.  Field Assisted Glass‐Metal Sealing , 1969 .

[71]  Jan-Åke Schweitz,et al.  Bulk and surface micromachining of GaAs structures , 1990, IEEE Proceedings on Micro Electro Mechanical Systems, An Investigation of Micro Structures, Sensors, Actuators, Machines and Robots..

[72]  Herbert Reichl,et al.  High power multichip modules employing the planar embedding technique and microchannel water heat sinks , 1997, Thirteenth Annual IEEE. Semiconductor Thermal Measurement and Management Symposium.

[73]  Zhaonian Cheng,et al.  The effects of underfill and its material models on thermomechanical behaviors of a flip chip package , 2001 .

[74]  J.-Q. Lu,et al.  Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform , 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).

[75]  James D. Meindl,et al.  Cost analysis of compliant wafer level package , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[76]  R. Prasher,et al.  Thermal contact resistance of cured gel polymeric thermal interface material , 2004, IEEE Transactions on Components and Packaging Technologies.

[77]  Lianhua Fan,et al.  Adhesion/reliability/reworkability study on underfill material from free radical polymerization system and its hybrid composite with epoxy resin , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[78]  R. Pease,et al.  High-performance heat sinking for VLSI , 1981, IEEE Electron Device Letters.

[79]  Muhannad S. Bakir Sea of Leads electrical-optical polymer pillar chip I/O interconnections for gigascale integration , 2003 .

[80]  J. Meindl,et al.  Wafer-level microfluidic cooling interconnects for GSI , 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..

[81]  E. Colgan,et al.  A practical implementation of silicon microchannel coolers for high power chips , 2005, Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005..

[82]  Muhannad S. Bakir,et al.  Sea of polymer pillars: dual-mode electrical-optical Input/Output interconnections , 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).

[83]  A. Wego,et al.  Fluidic microsystems based on printed circuit board technology , 2001 .

[84]  M. Baelmans,et al.  On-Chip Liquid Cooling With Integrated Pump Technology , 2007, IEEE Transactions on Components and Packaging Technologies.

[85]  A. B. Frazier,et al.  A low temperature IC compatible process for fabricating surface micromachined metallic microchannels , 1997, Proceedings IEEE The Tenth Annual International Workshop on Micro Electro Mechanical Systems. An Investigation of Micro Structures, Sensors, Actuators, Machines and Robots.

[86]  Bing Dang,et al.  Chip integration of Sea of Leads compliant I/O interconnections for the ultimate enabling of chips with low-k interlayer dielectrics , 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).

[87]  Qi Zhu Helix-type compliant off-chip interconnect for microelectronic packaging , 2003 .

[88]  Ioan Sauciuc,et al.  Thermal Performance and Key Challenges for Future CPU Cooling Technologies , 2005 .

[89]  C.G. Fonstad,et al.  Preparation of silicon-on-gallium arsenide wafers for monolithic optoelectronic integration , 1999, IEEE Photonics Technology Letters.

[90]  H. N. Keller,et al.  Solder Connections with a Ni Barrier , 1986 .

[91]  S. Kandlikar,et al.  Extending the heat flux limit with enhanced microchannels in direct single-phase cooling of computer chips , 2005, Semiconductor Thermal Measurement and Management IEEE Twenty First Annual IEEE Symposium, 2005..

[92]  Muhannad S. Bakir,et al.  Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI) , 2003 .

[93]  K. Chan,et al.  Investigation of Cr/Cu/Cu/Ni under bump metallization for lead-free applications , 2002, 4th Electronics Packaging Technology Conference, 2002..

[94]  R. Beach,et al.  Demonstration of high‐performance silicon microchannel heat exchangers for laser diode array cooling , 1988 .

[95]  M.J. Ellsworth,et al.  Review of cooling technologies for computer products , 2004, IEEE Transactions on Device and Materials Reliability.

[96]  Kaushik Roy,et al.  Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[97]  Anthony Victor Mule Volume grating coupler-based optical interconnect technologies for polylithic gigascale integrat , 2004 .

[98]  J. Meindl,et al.  Sea-of-leads MEMS I/O interconnects for low-k IC packaging , 2006, Journal of Microelectromechanical Systems.

[99]  David A. B. Miller,et al.  Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture , 1997, J. Parallel Distributed Comput..

[100]  L. L. Mercado,et al.  Impact of flip-chip packaging on copper/low-k structures , 2003 .

[101]  Dong Liu,et al.  Analysis and Optimization of the Thermal Performance of Microchannel Heat Sinks , 2003 .