论文信息 - Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I/O's Using Fault Injection on SRAM Based FPGAs

Characterization of Upset-Induced Degradation of Error-Mitigated High-Speed I/O's Using Fault Injection on SRAM Based FPGAs

Fault-injection experiments on Virtex-IItrade FPGAs quantify failure and degradation modes in I/O channels incorporating triple module redundancy (TMR). With increasing frequency (to 100 MHz), full TMR under both I/O standards investigated (LVCMOS at 3.3V and 1.8V) shows more configuration bits have a measurable detrimental performance effect when in error

S. Rezgui | G.M. Swift | A. Lesea

[1] C. Carmichael,et al. Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs) , 2004, IEEE Transactions on Nuclear Science.

[2] Carl Carmichael,et al. Triple Module Redundancy Design Techniques for Virtex FPGAs, Application Note 197 , 2001 .

[3] C. Carmichael,et al. SEU mitigation testing of Xilinx Virtex II FPGAs , 2003, 2003 IEEE Radiation Effects Data Workshop.