Latch-up free ESD protection design with SCR structure in advanced CMOS technology

An electrostatic discharge (ESD) protection circuit with silicon-controlled-rectifier (SCR) device has been designed without latch-up risk. After fabrication in a 0.13-µm CMOS process, the ESD protection circuit with SCR width of 60µm can sustain 6.2kV human-body-model (HBM) and 475V machine model (MM) ESD tests. The latch-up test shows the immunity against 500-mA triggering current under 3.3V supply voltage.

[1]  R. Gauthier,et al.  Evaluation of SCR-Based ESD Protection Devices in 90nm and 65nm CMOS Technologies , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[2]  M. Mergens,et al.  Diode-triggered SCR (DTSCR) for RF-ESD protection of BiCMOS SiGe HBTs and CMOS ultra-thin gate oxides , 2003, IEEE International Electron Devices Meeting 2003.

[3]  Guido Notermans,et al.  Using an SCR as ESD protection without latch-up danger , 1997 .

[4]  C.C. Russ,et al.  GGSCRs: GGNMOS Triggered silicon controlled rectifiers for ESD protection in deep sub-micron CMOS processes , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[5]  Ming-Dou Ker,et al.  Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits , 2005, IEEE Transactions on Device and Materials Reliability.

[6]  O. Marichal,et al.  Characterizing the transient device behavior of SCRs by means of VFTLP waveform analysis , 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

[7]  S.H. Voldman,et al.  RC-triggered PNP and NPN simultaneously switched silicon controlled rectifier ESD networks for sub-0.18/spl mu/m technology , 2005, Proceedings of the 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2005. IPFA 2005..

[8]  Koen G. Verhaege,et al.  High Holding Current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation , 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.

[9]  T. Polgreen,et al.  A low-voltage triggering SCR for on-chip ESD protection at output and input pads , 1990, IEEE Electron Device Letters.

[10]  G. Meneghesso,et al.  Development of a new high holding voltage SCR-based ESD protection structure , 2008, 2008 IEEE International Reliability Physics Symposium.