A reconfigurable memory architecture for system integration of coarse-grained reconfigurable arrays

Coarse-Grained Reconfigurable Arrays (CGRAs) have emerged as a powerful solution to speed up computationally intensive applications. Heterogeneous MPSoC architectures containing such reconfigurable accelerators have the advantage of providing greater flexibility, power-efficiency, and high performance. However, CGRAs may suffer from a data access bottleneck. To mitigate this problem, we present a reconfigurable memory architecture for CGRAs. Here, buffers can be configured at runtime to select between different schemes for memory access, i. e., random access memory or pixel buffers. We showcase the benefits to our approach by prototyping a heterogeneous MPSoC architecture containing a RISC processor and a class of CGRAs called tightly coupled processor arrays (TCPAs). The architecture is prototyped in FPGA technology. To communicate with up to 32 processing elements (PEs), the memory architecture utilizes less than 2.5% of slice registers and LUTs available in a Virtex-7 XC7V2000. For digital signal processing applications, we demonstrate that our solution for system integration allows increasing the memory bandwidth utilization in comparison to state-of-the-art solutions for image processing.

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