Flexible escape routing for flip-chip designs
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[1] R. C. Frye,et al. Flip-chip and chip-scale I/O density requirements and printed wiring board capabilities , 1997, 1997 Proceedings 47th Electronic Components and Technology Conference.
[2] Bidyut K. Bhattacharyya,et al. A method of designing a group of bumps for C4 packages to maximize the number of bumps and minimize the number of package layers , 1994, 1994 Proceedings. 44th Electronic Components and Technology Conference.
[3] Y. Takeuchi,et al. Escape routing design to reduce the number of layers in area array packaging , 2000 .
[4] E. Winkler. Escape routing from chip scale packages , 1996, Nineteenth IEEE/CPMT International Electronics Manufacturing Technology Symposium.
[5] A. Titus,et al. Innovative circuit board level routing designs for BGA packages , 2004, IEEE Transactions on Advanced Packaging.
[6] Rui Shi,et al. Efficient escape routing for hexagonal array of high density I/Os , 2006, 2006 43rd ACM/IEEE Design Automation Conference.