A Tutorial on Uppaal

This is a tutorial paper on the tool Uppaal. Its goal is to be a short introduction on the flavor of timed automata implemented in the tool, to present its interface, and to explain how to use the tool. The contribution of the paper is to provide reference examples and modeling patterns.

[1]  Alexandre David,et al.  Hierarchical modeling and analysis of timed systems , 2003 .

[2]  Diego Latella,et al.  Automatic Veri cation of a Lip Synchronisation Algorithm using Uppaal , 1998 .

[3]  Wang Yi,et al.  A Generic Approach to Schedulability Analysis of Real-Time Tasks , 2004, Nord. J. Comput..

[4]  Kim G. Larsen,et al.  Guided Synthesis of Control Programs Using UPPAAL , 2000, Nord. J. Comput..

[5]  Kim G. Larsen,et al.  The power of reachability testing for timed automata , 1998, Theor. Comput. Sci..

[6]  Gerd Behrmann,et al.  Efficient Guiding Towards Cost-Optimality in UPPAAL , 2001, TACAS.

[7]  Wang Yi,et al.  UPPAAL Implementation Secrets , 2002, FTRTFT.

[8]  Lars Michael Kristensen,et al.  A Generalised Sweep-Line Method for Safety Properties , 2002, FME.

[9]  Rajeev Alur,et al.  Model-checking for real-time systems , 1990, [1990] Proceedings. Fifth Annual IEEE Symposium on Logic in Computer Science.

[10]  Diego Latella,et al.  Automatic Verification of a Lip-Synchronisation Protocol Using Uppaal , 1998, Formal Aspects of Computing.

[11]  Frits W. Vaandrager,et al.  Analysis of a biphase mark protocol with Uppaal and PVS , 2006, Formal Aspects of Computing.

[12]  Joost P. Katoen,et al.  Concepts, Algorithms, and Tools for Model Checking , 1999 .

[13]  Joost-Pieter Katoen,et al.  A probabilistic extension of UML statecharts: Specification and Verification. , 2002 .

[14]  Kim G. Larsen,et al.  Exact Acceleration of Real-Time Model Checking , 2002, Theory and Practice of Timed Systems @ ETAPS.

[15]  Brian Nielsen.  Specification and Test of Real-Time Systems , 2000 .

[16]  Wang Yi,et al.  Workshop on Real-Time Tools , 2002 .

[17]  Wang Yi,et al.  Partial Order Reductions for Timed Systems , 1998, CONCUR.

[18]  Paul Pettersson.  Modelling and Verification of Real-Time Systems Using Timed Automata : Theory and Practice , 1999 .

[19]  Wang Yi,et al.  A Tool Architecture for the Next Generation of Uppaal , 2002, 10th Anniversary Colloquium of UNU/IIST.

[20]  David Maier,et al.  Review of "Introduction to automata theory, languages and computation" by John E. Hopcroft and Jeffrey D. Ullman. Addison-Wesley 1979. , 1980, SIGA.

[21]  Wang Yi,et al.  New Generation of UPPAAL , 1998 .

[22]  Wang Yi,et al.  Uppaal in a nutshell , 1997, International Journal on Software Tools for Technology Transfer.

[23]  Elena Fersman.  Generic Approach to Schedulability Analysis of Real-Time Systems (Uppsala Dissertations from the Faculty of Science & Technology, 49) , 2003 .

[24]  Wang Yi,et al.  Unification & Sharing in Timed Automata Verification , 2003, SPIN.

[25]  Gerard J. Holzmann.  An analysis of bitstate hashing , 1995 .

[26]  Kare Jelling Kristoffersen,et al.  Compositional Verification of Concurrent Systems , 1998 .

[27]  Wang Yi,et al.  UPPAAL - Now, Next, and Future , 2000, MOVEP.

[28]  Gerd Behrmann,et al.  Adding Symmetry Reduction to Uppaal , 2003, FORMATS.

[29]  Claude Jard,et al.  Modeling and Verification of Parallel Processes , 2001, Lecture Notes in Computer Science.

[30]  Mariëlle Stoelinga,et al.  Mechanical verification of the IEEE 1394a root contention protocol using Uppaal2k , 2001, International Journal on Software Tools for Technology Transfer.

[31]  Perdita Stevens,et al.  Modelling Recursive Calls with UML State Diagrams , 2003, FASE.

[32]  Alan Bundy,et al.  Constructing Induction Rules for Deductive Synthesis Proofs , 2006, CLASE.

[33]  Ansgar Fehnker,et al.  Citius, Vilius, Melius : guiding and cost-optimality in model checking of timed and hybrid systems , 2002 .

[34]  Wang Yi,et al.  Modelling and analysis of a commercial field bus protocol , 2000, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS 2000.

[35]  Rajeev Alur,et al.  A Temporal Logic of Nested Calls and Returns , 2004, TACAS.

[36]  Frits W. Vaandrager,et al.  Distributing Timed Model Checking - How the Search Order Matters , 2000, CAV.

[37]  Kim G. Larsen,et al.  Formal Verification of a Power Controller Using the Real-Time Model Checker UPPAAL , 1999, ARTS.

[38]  Wang Yi,et al.  TIMES - A Tool for Modelling and Implementation of Embedded Systems , 2002, TACAS.

[39]  Wang Yi,et al.  New UPPAAL Architecture , 2002 .

[40]  Gerd Behrmann,et al.  Distributed reachability analysis in timed automata , 2005, International Journal on Software Tools for Technology Transfer.

[41]  Martin Peschke,et al.  Design and Validation of Computer Protocols , 2003 .

[42]  Wang Yi,et al.  UPPAAL - present and future , 2001, Proceedings of the 40th IEEE Conference on Decision and Control (Cat. No.01CH37228).

[43]  Jeffrey D. Ullman,et al.  Introduction to Automata Theory, Languages and Computation , 1979 .

[44]  Wang Yi,et al.  Efficient Timed Reachability Analysis Using Clock Difference Diagrams , 1998, CAV.

[45]  Wang Yi,et al.  Formal Verification of UML Statecharts with Real-Time Extensions , 2002, FASE.

[46]  Kim G. Larsen,et al.  Model-checking real-time control programs: verifying LEGO MINDSTORMSTM systems using UPPAAL , 2000, Proceedings 12th Euromicro Conference on Real-Time Systems. Euromicro RTS 2000.

[47]  Kim G. Larsen,et al.  Scaling up Uppaal Automatic Verification of Real-Time Systems Using Compositionality and Abstraction , 2000, FTRTFT.

[48]  Elena Fersman,et al.  A Generic Approach to Schedulability Analysis of Real-Time Systems , 2003 .

[49]  Kim Guldstrand Larsen,et al.  Model-Checking Real-Time Control Programs. Verifying LEGO Mindstorms Systems Using UPPAAL , 1999 .

[50]  Stephen Gilmore,et al.  Specifying Performance Measures for PEPA , 1999, ARTS.

[51]  Johan Bengtsson,et al.  Clocks, DBMS and States in Timed Systems , 2002 .

[52]  Kim G. Larsen,et al.  Minimum-Cost Reachability for Priced Timed Automata , 2001, HSCC.

[53]  Satoshi Yamane,et al.  The symbolic model-checking for real-time systems , 1996, Proceedings of the Eighth Euromicro Workshop on Real-Time Systems.

[54]  Robin Milner,et al.  On Observing Nondeterminism and Concurrency , 1980, ICALP.

[55]  Hans Toetenel.  Proceedings of the 12th Euromicro conference on Real-time systems , 2000 .

[56]  Philippe Schnoebelen,et al.  Systems and Software Verification , 2001, Springer Berlin Heidelberg.

[57]  Arne Skou,et al.  Formal Modeling and Analysis of an Audio/Video Protocol: An Industrial Case Study Using UPPAAL , 1997 .

[58]  Wang Yi,et al.  Automatic verification of real-time communicating systems by constraint-solving , 1994, FORTE.

[59]  守屋 悦朗,et al.  J.E.Hopcroft, J.D. Ullman 著, "Introduction to Automata Theory, Languages, and Computation", Addison-Wesley, A5変形版, X+418, \6,670, 1979 , 1980 .

[60]  Kim G. Larsen,et al.  As Cheap as Possible: Efficient Cost-Optimal Reachability for Priced Timed Automata , 2001, CAV.

[61]  Biniam Gebremichael,et al.  A formal analysis of a car periphery supervison system 1 , 2004 .

[62]  Kim G. Larsen,et al.  Lower and upper bounds in zone-based abstractions of timed automata , 2004, International Journal on Software Tools for Technology Transfer.

[63]  Felice Balarin,et al.  Approximate reachability analysis of timed automata , 1996, 17th IEEE Real-Time Systems Symposium.

[64]  Kim G. Larsen,et al.  Model Checking via Reachability Testing for Timed Automata , 1997, TACAS.

[65]  Thomas A. Henzinger,et al.  Hybrid Systems: Computation and Control , 1998, Lecture Notes in Computer Science.

[66]  Frits W. Vaandrager,et al.  Model checker aided design of a controller for a wafer scanner , 2006, International Journal on Software Tools for Technology Transfer.

[67]  Theo C. Ruys,et al.  The Bounded Retransmission Protocol Must Be on Time! , 1997, TACAS.

[68]  H. Lonn,et al.  Formal verification of a TDMA protocol start-up mechanism , 1997, Proceedings Pacific Rim International Symposium on Fault-Tolerant Systems.

[69]  Philippe Schnoebelen,et al.  Systems and Software Verification, Model-Checking Techniques and Tools , 2001 .

[70]  Wang Yi,et al.  Efficient verification of real-time systems: compact data structure and state-space reduction , 1997, Proceedings Real-Time Systems Symposium.

[71]  Wang Yi,et al.  Formal design and analysis of a gear controller , 1998, International Journal on Software Tools for Technology Transfer.