Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip

Network-on-Chip (NoC) is a promising solution for System-on-Chip (SoC) challenges. In this work, we present a Decompose and Cluster generation Refinement (DCR) algorithm to find minimum power consumption simultaneously. A two-stage method is proposed for decompose and cluster generation step to generate solutions with lower power. Refinement step explores optimal positions and adjusts clusters for selected solutions to find balanced point between power consumption and CPU time. Experimental results show that the proposed method outperforms the existing work.

[1]  Sharad Malik,et al.  Orion: a power-performance simulator for interconnection networks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[2]  Shashi Shekhar,et al.  Multilevel hypergraph partitioning: applications in VLSI domain , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Satoshi Goto,et al.  Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips , 2013, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[4]  Takeshi Yoshimura,et al.  Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Wei Zhong,et al.  Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips , 2012, IEICE Trans. Electron..