A Reconfigurable 10-12 b 0 . 4-44 MS / s Pipelined ADC with 0 . 35-0 . 5 pJ / step in 1 . 2 V 90 nm Digital CMOS

I. INTRODUCTION The growing demand for multi-mode/multi-standard wireless terminals is fuelling interest in ADCs that are reconfigurable over a wide range of bandwidths BW and resolutions N. Furthermore, for power-efficiency, these ADCs must be power-scalable (i.e., their power scales with their BW and N), thereby maintaining a constant figure-of-merit (FOM) over their entire reconfigurability space. A ΔΣ ADC can only be reconfigured to discrete bandwidth-resolution modes (covering specific radio standards), due to the strong interdependence between its bandwidth and its resolution. Thus, a pipelined ADC is more attractive for reconfigurability, as it can be reconfigured over a continuous range of bandwidths, for each setting of its resolution. This pipelined ADC is reconfigurable over a continuous range of sampling frequencies (bandwidths), for resolutions. Fabricated in 1.2-V 90-nm digital CMOS, it achieves an over its full bandwidth-resolution space. Thus, this ADC is suitable for multiple wireless and cellular standards, ranging from GSM up to LTE/WiMax and 802.11g. Furthermore, owing to its power efficiency, this ADC is attractive for various applications over a wide bandwidth-resolution space, thereby saving on development costs and reducing the time-to-market. Compared to the state-of-the-art power-efficient reconfigurable pipelined (Fig. 10a) or ΔΣ (Fig. 10b) ADCs, this ADC provides a wide bandwidth-resolution reconfigurability space, while maintaining the most competitive FOM over this entire space. Furthermore, at its maximum speed and maximum resolution setting, this ADC achieves an FOM that is among the most competitive compared to the FOMs of non-reconfigurable pipelined