Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations
暂无分享,去创建一个
Donggyu Kim | Adam M. Izraelevitz | Jonathan Bachrach | Angie Wang | Jim Lawson | Patrick Li | Chick Markley | Colin Schmidt | Jack Koenig | Richard Lin | Albert Magyar | J. Bachrach | Chick Markley | Donggyu Kim | Jack Koenig | Albert Magyar | Colin Schmidt | Angie Wang | Richard Lin | Patrick Li | Jim Lawson
[1] Mark Horowitz,et al. Avoiding game over: Bringing design to the next level , 2012, DAC Design Automation Conference 2012.
[2] Muhsen Owaida,et al. Synthesis of Platform Architectures from OpenCL Programs , 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.
[3] Jan Decaluwe. MyHDL: a python-based hardware description language , 2004 .
[4] Rishiyur S. Nikhil,et al. Bluespec System Verilog: efficient, correct RTL from high level specifications , 2004, Proceedings. Second ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2004. MEMOCODE '04..
[5] Mark Horowitz,et al. Rethinking Digital Design: Why Design Must Change , 2010, IEEE Micro.
[6] Erik R. Altman. Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems , 2008 .
[7] Maya Gokhale,et al. Trident: From High-Level Language to Hardware Circuitry , 2007, Computer.
[8] Christoforos E. Kozyrakis,et al. Understanding sources of inefficiency in general-purpose chips , 2010, ISCA.
[9] Joshua S. Auerbach,et al. Lime: a Java-compatible and synthesizable language for heterogeneous architectures , 2010, OOPSLA.
[10] Jason Helge Anderson,et al. LegUp: high-level synthesis for FPGA-based processor/accelerator systems , 2011, FPGA '11.
[11] Jeffrey Heer,et al. D³ Data-Driven Documents , 2011, IEEE Transactions on Visualization and Computer Graphics.
[12] John Wawrzynek,et al. Chisel: Constructing hardware in a Scala embedded language , 2012, DAC Design Automation Conference 2012.
[13] Mark Horowitz,et al. Vex—A CAD toolbox , 1999, DAC '99.
[14] Vazgen Melikyan,et al. Synopsys' open educational design kit: Capabilities, deployment and future , 2009, 2009 IEEE International Conference on Microelectronic Systems Education.
[15] David Wentzlaff,et al. OpenPiton: An Open Source Manycore Research Framework , 2016, ASPLOS.
[16] Shinya Takamaeda-Yamazaki,et al. Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL , 2015, ARC.
[17] Brad L. Hutchings,et al. JHDL-an HDL for reconfigurable systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).
[18] Jason Cong,et al. FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs , 2009, 2009 IEEE 7th Symposium on Application Specific Processors.
[19] Miriam Leeser,et al. HML, a novel hardware description language and its translation to VHDL , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[20] John Freeman,et al. From opencl to high-performance hardware on FPGAS , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).
[21] Eric Senn,et al. ∂ GAUT: A High-Level Synthesis Tool for DSP applications , 2008 .
[22] Kenji Kise,et al. ArchHDL: A Novel Hardware RTL Design Environment in C++ , 2015, ARC.
[23] Steven Swanson,et al. Conservation cores: reducing the energy of mature computations , 2010, ASPLOS XV.
[24] Adam M. Izraelevitz,et al. The Rocket Chip Generator , 2016 .
[25] Scott A. Mahlke,et al. Optimus: efficient realization of streaming applications on FPGAs , 2008, CASES '08.
[26] Hokeun Kim,et al. Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).
[27] Martin Odersky,et al. An Overview of the Scala Programming Language , 2004 .
[28] David A. Patterson,et al. The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor , 2015 .
[29] Kunle Olukotun,et al. Hardware system synthesis from Domain-Specific Languages , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).
[30] Vikram Bhatt,et al. The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future , 2011, IEEE Micro.
[31] Jürgen Teich,et al. PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications , 2008, ARC.
[32] Vikram S. Adve,et al. LLVM: a compilation framework for lifelong program analysis & transformation , 2004, International Symposium on Code Generation and Optimization, 2004. CGO 2004..
[33] Christopher Batten,et al. PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[34] Jeffrey Heer,et al. SpanningAspectRatioBank Easing FunctionS ArrayIn ColorIn Date Interpolator MatrixInterpola NumObjecPointI Rectang ISchedu Parallel Pause Scheduler Sequen Transition Transitioner Transiti Tween Co DelimGraphMLCon IData JSONCon DataField DataSc Dat DataSource Data DataUtil DirtySprite LineS RectSprite , 2011 .
[35] Franz Franchetti,et al. Computer Generation of Hardware for Linear Digital Signal Processing Transforms , 2012, TODE.