Avoiding wafer-print artifacts in spacer is dielectric (SID) patterning
暂无分享,去创建一个
For patterning the upper Metal layers of the 10 nm node, Spacer Is Dielectric (SID) Patterning is the leading candidate. Compared to Litho-Etch-Litho-Etch Double Patterning, SID has lower line-width roughness, tighter line-end spacing, and lower sensitivity to overlay errors. However, SID places more restrictions on design, and creates wafer-printing artifacts or “spurs.” These printing artifacts arise because SID uses a subtractive trim etch to create “negative contours,” which are very different from the positive contours of single-exposure patterning. In this work, we show the origin of these spurs, and present rule-based decomposition methods to avoid or mitigate them.
[1] Hongbo Zhang,et al. Hot spot detection for indecomposable self-aligned double patterning layout , 2011, Photomask Technology.
[2] David Z. Pan,et al. Layout decomposition of self-aligned double patterning for 2D random logic patterning , 2011, Advanced Lithography.
[3] Li Lin,et al. Design compliance for spacer is dielectric (SID) patterning , 2012, Advanced Lithography.