论文信息 - A 28.5mW 2.8GFLOPS floating-point multifunction unit for handheld 3D graphics processors

A 28.5mW 2.8GFLOPS floating-point multifunction unit for handheld 3D graphics processors

A low-power, high-performance 4-way 32-bit floating-point multifunction unit is developed for handheld 3D graphics processors. It uses logarithmic arithmetic to unify matrix, vector, and elementary functions into a single arithmetic unit. The optimal designs of logarithmic and antilogarithmic converters are presented. An adaptive number conversion scheme is proposed and it reduces total area by 15%. With this scheme, the matrix-vector multiplication (MAT), cross-product, lerp, and logarithm (logx y with 2 variables) are newly unified with the other operations. The unit achieves 2-cycle throughput for the MAT and single-cycle throughput for all other operations. It takes 451 K transistors and achieves 2.8 GFLOPS at 200 MHz with 28.5 mW power consumption.

Hoi-Jun Yoo | Byeong-Gyu Nam

[1] Fumio Arakawa,et al. An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU , 2004 .

[2] Hoi-Jun Yoo,et al. A 210MHz 15mW Unified Vector and Transcendental Function Unit for Handield 3-D Graphics Systems , 2006, 2006 IEEE Asian Solid-State Circuits Conference.

[3] Byeong-Gyu Nam. A 210MHz 5mW UnifiedVector and Transcendental Function UnitforHandield 3-D , 2006 .

[4] Ching-Farn Eric Wu,et al. A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities , 1991, IEEE Trans. Computers.

[5] Hoi-Jun Yoo,et al. A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6] S.H. Dhong,et al. A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor , 2006, IEEE Journal of Solid-State Circuits.