Using an MDE Approach for Modeling of Interconnection Networks

As system-on-chip (SoCs) become more complex, high performance interconnection mediums are required to handle their complexity. Network-on-chips (NoCs) enable integration of more intellectual properties (IPs) into the SoC with increased performance. In the recent MARTE (modeling and analysis of real-time and embedded systems) profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topologies. This paper presents a modeling methodology based on that notation to model the delta network family of interconnection networks for NoC construction.

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