The Design of Novel Dual Modulus Divider-by 32/33 Prescaler

In this paper, a novel design plan of divider was presented. In the higher frequency band, M/S DFF structured by CMOS SCL were used to divider; In the lower frequency band, DFF with self-latch function were used to implement High-Speed Low-Power Low-Jitter Dual Modulus Divider-by 32/33 Prescaler. The circuit was simulated by Cadence Spectre under the CMOS technology of TSMC 0.18um. It has shown that the highest frequency of the divider is up to 5GHz. When T=27℃,VDD=1.8V, f=5GHz, the power consumption of the circuit was only 4.32mW(1.8V×2.4mA).