Challenges and Methodologies for Implementing High-Performance Network Processors

Moore’s law has been the guiding principle for performance and transistor density improvements over the years. While this is true, in the context of network processor development, the challenge is multi-faceted to keep the silicon development on the curve. This paper describes the challenges for a network processor implementation in each facet of design. The network processor designs adopted the following implementation techniques to manage the design challenges and the Time-to-Market (TTM) schedule: • Reuse of Intellectual Property (IP). • Extensive functional validation. • High-performance clock architecture and design. • Streamlined hierarchical physical design flow. • Efficient and cycle-accurate c-model for performance simulation. A case study of implementation on the IXP2400 design is presented with the above strategies in detail. The silicon results show that the IXP2400 is a successful design following the stated methods.