THE EFFECT OF LOGIC BLOCK GRANULARITY ON DEEP-SUBMICRON FPGA PERFORMANCE AND DENSITY

The Effect of Logic Block Granularity on Deep-Submicron FPGA Performance and Density Elias Ahmed Master of Applied Science Graduate Department of Electricd and Computer Engineering University of Toronto

[1]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[2]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[3]  Vaughn Betz,et al.  Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density , 1999, FPGA '99.

[4]  Jonathan Rose,et al.  The effect of logic block complexity on area of programmable gate arrays , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[5]  Bai Nguyen,et al.  An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-Gating Functions , 1999, FPGA.

[6]  Jason Cong,et al.  Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation , 1998, FPGA '98.

[7]  Jason Cong,et al.  RASP: A General Logic Synthesis System for SRAM-Based FPGAs , 1996, Fourth International ACM Symposium on Field-Programmable Gate Arrays.

[8]  A. El Gamal,et al.  FPGA performance versus cell granularity , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[9]  Pierre Marchal,et al.  Field-programmable gate arrays , 1999, CACM.

[10]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[11]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  Jonathan Rose,et al.  The effect of logic block architecture on FPGA performance , 1992 .

[13]  Sinan Kaptanoglu,et al.  A new high density and very low cost reprogrammable FPGA architecture , 1999, FPGA '99.

[14]  Kevin Charles Kenton Chung.  Architecture and Synthesis of Field-Programmable Gate Arrays with Hard-wired Connections , 1994 .

[15]  Vaughn Betz,et al.  How Much Logic Should Go in an FPGA Logic Block? , 1998, IEEE Des. Test Comput..

[16]  Jonathan Rose,et al.  CALL FOR ARTICLES IEEE Design & Test of Computers Special Issue on Microprocessors , 1996 .

[17]  A. El Gamal,et al.  PLA-based FPGA Area Versus Cell C+ Granularity , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[18]  Jonathan Rose,et al.  Architecture of field-programmable gate arrays: the effect of logic block functionality on area efficiency , 1990 .

[19]  Alexander R. Marquardt,et al.  Cluster-Based Architecture, Timing-Driven Packing and Timing-Driven Placement for FPGAs , 1999 .

[20]  Vaughn Betz,et al.  Cluster-based logic blocks for FPGAs: area-efficiency vs. input sharing and size , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.