Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget

Abstract Fault security indicates ability to provide error detection or fetch correct output. Fault security assures possibility of using either hardware redundancy or time redundancy to optimize the overheads associated with fault security. However, generation (design space exploration (DSE)) of an optimal fault secured datapath structure based on user power–delay budget during high level synthesis (HLS) in the context k-cycle transient fault is considered an intractable problem. This is due to the fact that for every type of candidate design solution produced during exploration, a feasible k-cycle fault secured datapath may not exist which satisfies the conflicting user constraints/budget. Secondly, insertion of inapt cut (resulting in an additional checkpoint) to optimize delay overhead associated with fault security in most cases may not result in optimal solutions in the context of user constraints/budgets. The solutions to the above problems have not been addressed in the literature so far. The paper therefore presents the following novelties: (a) an algorithm for fault secured DSE process (b) handling k-cycle transient faults during DSE (c) schemes for selecting appropriate edges for inserting cuts that selects available locations in the scheduled Control Data Flow Graph (CDFG) which minimizes delay overhead associated with fault security (d) swarm intelligence (particle swarm optimization) driven DSE process that adaptively/intelligently computes the candidate design solutions for generating an optimal fault secured datapath. Results of the proposed approach when tested on standard benchmarks yielded optimal results in most cases as evident from the data obtained for generational distance (GD), spacing (S), spreading (Δ) and weighted metric (Wm). Further, results of comparison with a recent approaches indicated significant reduction of final cost (better quality) for the proposed approach.

[1]  Ramesh Karri,et al.  Transformation-based high-level synthesis of fault-tolerant ASICs , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[2]  Luca P. Carloni,et al.  On learning-based methods for design-space exploration with High-Level Synthesis , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[3]  Chittaranjan A. Mandal,et al.  GABIND: a GA approach to allocation and binding for the high-level synthesis of data paths , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[4]  P. Dodd,et al.  Production and propagation of single-event transients in high-speed digital logic ICs , 2004, IEEE Transactions on Nuclear Science.

[5]  Kishor S. Trivedi,et al.  Reliability estimation of fault-tolerant systems: tools and techniques , 1990, Computer.

[6]  Philippe Coussy,et al.  Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[7]  Ramesh Karri,et al.  Fault secure datapath synthesis using hybrid time and hardware redundancy , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Reza Sedaghat,et al.  A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels , 2012, Swarm Evol. Comput..

[9]  Mark Zwolinski,et al.  An Integrated High-Level On-Line Test Synthesis Tool , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  Reza Sedaghat,et al.  A framework for fast design space exploration using fuzzy search for VLSI computing Architectures , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

[11]  Ioan Cristian Trelea,et al.  The particle swarm optimization algorithm: convergence analysis and parameter selection , 2003, Inf. Process. Lett..

[12]  Anirban Sengupta,et al.  Automated exploration of datapath and unrolling factor during power-performance tradeoff in architectural synthesis using multi-dimensional PSO algorithm , 2014, Expert Syst. Appl..

[13]  Daniele Loiacono,et al.  A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[14]  Niraj K. Jha,et al.  Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis , 2000, IEEE Trans. Computers.

[15]  Srinivas Katkoori,et al.  A genetic algorithm for the design space exploration of datapaths during high-level synthesis , 2006, IEEE Transactions on Evolutionary Computation.

[16]  Robert H. Storer,et al.  Datapath synthesis using a problem-space genetic algorithm , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Jacob A. Abraham,et al.  Fault-Tolerant FFT Networks , 1988, IEEE Trans. Computers.

[18]  Dhiraj K. Pradhan,et al.  High level synthesis of data driven ASICs , 1991, [1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit.

[19]  Parag K. Lala,et al.  Fault tolerant and fault testable hardware design , 1985 .

[20]  Kalyanmoy Deb,et al.  Multi-objective optimization using evolutionary algorithms , 2001, Wiley-Interscience series in systems and optimization.

[21]  John A. Nestor,et al.  SALSA: a new approach to scheduling with timing constraints , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Anirban Sengupta,et al.  MO-PSE: Adaptive multi-objective particle swarm optimization based design space exploration in architectural synthesis for application specific processor design , 2014, Adv. Eng. Softw..

[23]  Reza Sedaghat,et al.  Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems , 2011, Microelectron. Reliab..

[24]  Mark Zwolinski,et al.  Simultaneous optimisation of dynamic power, area and delay in behavioural synthesis , 2000 .

[25]  E. Torbey,et al.  Performing scheduling and storage optimization simultaneously using genetic algorithms , 1998, 1998 Midwest Symposium on Circuits and Systems (Cat. No. 98CB36268).

[26]  James Kennedy,et al.  Particle swarm optimization , 2002, Proceedings of ICNN'95 - International Conference on Neural Networks.

[27]  Anirban Sengupta,et al.  Design Space Exploration of Datapath (Architecture) in High-Level Synthesis for Computation Intensive Applications , 2015 .

[28]  Luigi Carro,et al.  System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies , 2007, 12th IEEE European Test Symposium (ETS'07).

[29]  Jason Cong,et al.  AutoPilot: A Platform-Based ESL Synthesis System , 2008 .

[30]  Yuhui Shi,et al.  Particle swarm optimization: developments, applications and resources , 2001, Proceedings of the 2001 Congress on Evolutionary Computation (IEEE Cat. No.01TH8546).

[31]  E. Normand Single-event effects in avionics , 1996 .

[32]  Miroslaw Malek,et al.  A Fault-Tolerant FFT Processor , 1988, IEEE Trans. Computers.

[33]  Zbigniew Michalewicz,et al.  Genetic Algorithms + Data Structures = Evolution Programs , 1996, Springer Berlin Heidelberg.

[34]  Reza Sedaghat,et al.  Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration , 2011, 2011 12th International Symposium on Quality Electronic Design.

[35]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[36]  Anirban Sengupta,et al.  Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis , 2014, Fifteenth International Symposium on Quality Electronic Design.

[37]  Christian Haubelt,et al.  SystemCoDesigner: Automatic design space exploration and rapid prototyping from behavioral models , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[38]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[39]  Ramesh Karri,et al.  Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors , 1996, IEEE Trans. Reliab..