Low power motion estimation design using adaptive pixel truncation

Power consumption is very critical for portable video applications such as portable video-phone. Motion estimation in the video encoder requires huge amount of computation and hence consumes the largest portion of power. In this paper we propose a novel method of reducing power consumption of the motion estimation by adaptively changing the pixel resolution during the computation of the motion vector. The pixel resolution is changed by masking or truncating the LSBs of the pixel data which is governed by an adaptive mechanism. Experimental results show that on average more than 4 bits can be truncated without affecting the picture quality. This results in an average 70% reduction in power consumption.

[1]  Peter Pirsch,et al.  VLSI architectures for video compression-a survey , 1995, Proc. IEEE.

[2]  I. Tamitani,et al.  A 1.5 W single-chip MPEG2 MP@ML encoder with low power motion estimation and clocking , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[3]  Karl M. Guttag,et al.  A single-chip multiprocessor for multimedia: the MVP , 1992, IEEE Computer Graphics and Applications.

[4]  Jan M. Rabaey,et al.  Power estimation for high level synthesis , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[5]  Ming-Ting Sun,et al.  A family of vlsi designs for the motion compensation block-matching algorithm , 1989 .

[6]  M. Liou,et al.  Reducing hardware complexity of motion estimation algorithms using truncated pixels , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[7]  Chi-Ying Tsui,et al.  Exploring the power consumption of different motion estimation architectures for video compression , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

[8]  Massoud Pedram,et al.  Statistical design of macro-models for RT-level power evaluation , 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.