QoS-ocMPI: QoS-aware on-chip Message Passing Library for NoC-based Many-Core MPSoCs

Homogeneous and heterogeneous NoC-based manycore MPSoCs are becoming widespread in many application areas. The diversity and spare network traffic characteristics generated by the IPs makes mandatory to provide certain Quality of Service (QoS) support for critical traffic streams on the system at application level even from the parallel programming model. In this paper, we present a hardware-software approach to enable QoS from the parallel programming model on the emerging NoC-based many-core MPSoCs. We designed NoC hardware QoS support, and the associated middleware API which enables runtime QoS on parallel programs. Additionally, a QoS-aware on-chip Message Passing Interface (ocMPI) stack is presented where QoS streams can be handled automatically on the system by means of task annotation on the ocMPI library, in order to distribute and balance workload under congestion, guaranteed throughput and latency bounds of critical processes and, in general to boost and meet QoS application requirements. Our experimental results during the execution of message passing parallel programs using prioritized and guaranteed services extensions on the QoS-aware ocMPI library show an average speedup of ≈15% and ≈35%, respectivelly.

[1]  L. Benini,et al.  Designing Application-Specific Networks on Chips with Floorplan Information , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[2]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.

[3]  Coniferous softwood GENERAL TERMS , 2003 .

[4]  D. Andreasson,et al.  On improving best-effort throughput by better utilization of guaranteed throughput channels in an on-chip communication system , 2004, Proceedings Norchip Conference, 2004..

[5]  Anant Agarwal,et al.  rMPI: Message Passing on Multicore Processors with On-Chip Interconnect , 2008, HiPEAC.

[6]  Ádamo L. de Santana,et al.  Towards the parallel computing based on quality of service , 2003, Second International Symposium on Parallel and Distributed Computing, 2003. Proceedings..

[7]  Théodore Marescaux,et al.  Introducing the SuperGT Network-on-Chip; SuperGT QoS: more than just GT , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[8]  Axel Jantsch,et al.  Networks on chip , 2003 .

[9]  Kees G. W. Goossens,et al.  Networks on silicon: combining best-effort and guaranteed services , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[10]  Georges Gielen,et al.  Design, Automation and Test in Europe Conference and Exhibition : Paris, France, February 16-20, 2004 , 2004 .

[11]  A. Skjellum,et al.  eMPI/eMPICH: embedding MPI , 1996, Proceedings. Second MPI Developer's Conference.

[12]  Kees G. W. Goossens,et al.  Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[13]  Everton Carara,et al.  Managing QoS flows at task level in NoC-based MPSoCs , 2009, 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC).

[14]  S. Borkar,et al.  An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[15]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[16]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[17]  Ali Afzali-Kusha,et al.  A new protocol stack model for network on chip , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

[18]  Soonhoi Ha,et al.  Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OS , 2007, 2007 Asia and South Pacific Design Automation Conference.

[19]  William Gropp,et al.  MPICH-GQ: Quality-of-Service for Message Passing Programs , 2000, ACM/IEEE SC 2000 Conference (SC'00).

[20]  Alberto L. Sangiovanni-Vincentelli,et al.  Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[21]  David Castells-Rufas,et al.  xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures , 2008, 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008).

[22]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[23]  L. Benini,et al.  Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.

[24]  Feng Liu,et al.  Extending OpenMP for heterogeneous chip multiprocessors , 2003, 2003 International Conference on Parallel Processing, 2003. Proceedings..

[25]  Luca Benini,et al.  MPARM: Exploring the Multi-Processor SoC Design Space with SystemC , 2005, J. VLSI Signal Process..

[26]  Sudhakar Yalamanchili,et al.  Interconnection Networks: An Engineering Approach , 2002 .

[27]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[28]  Axel Jantsch,et al.  The Nostrum backbone-a communication protocol stack for Networks on Chip , 2004, 17th International Conference on VLSI Design. Proceedings..

[29]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[30]  David Castells-Rufas,et al.  NocMaker: A cross-platform open-source design space exploration tool for networks on chip , 2009 .

[31]  Kees G. W. Goossens,et al.  Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip , 2003, DATE.

[32]  Paul Chow,et al.  TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[33]  Luca Benini,et al.  Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[34]  Luca Benini,et al.  Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips , 2006, 2006 IFIP International Conference on Very Large Scale Integration.

[35]  Barbara M. Chapman,et al.  Implementing OpenMP on a high performance embedded multicore MPSoC , 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

[36]  Federico Angiolini,et al.  /spl times/pipes Lite: a synthesis oriented design library for networks on chips , 2005, Design, Automation and Test in Europe.

[37]  H. Zimmermann,et al.  OSI Reference Model - The ISO Model of Architecture for Open Systems Interconnection , 1980, IEEE Transactions on Communications.