Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI

Nine D flip-flop architectures were implemented in 28nm FDSOI at a target, subthreshold, supply voltage of 200mV. The goal was to identify promising D flip-flops for ultra low power applications. The pass gate flip-flop was implemented using 49% of the S2CFF's area and was functional at the lowest operating voltage of 65mV in the typical process corner. At the targeted supply voltage of 200mV the racefree DFF gives the best functional yield of 99.8%. The flip-flops having the shortest D-Q delays were the PowerPC 603 and the transmission gate D flip-flop. These also had the lowest power delay products of 52.08aJ and 61.09aJ respectively.

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