Explicit-enumeration based verification made memory-efficient
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[1] Alan J. Hu,et al. Higher-Level Specification and Verification with BDDs , 1992, CAV.
[2] Somesh Jha,et al. Exploiting Symmetry In Temporal Logic Model Checking , 1993, CAV.
[3] Gerard J. Holzmann,et al. Design and validation of computer protocols , 1991 .
[4] Andreas J. Drexler,et al. Higher-level Speciication and Veriication with Bdds , 1993 .
[5] David L. Dill,et al. Better verification through symmetry , 1996, Formal Methods Syst. Des..
[6] Kedar S. Namjoshi,et al. Reasoning about rings , 1995, POPL '95.
[7] Steven D. Johnson. Synthesis of digital designs from recursion equations , 1983 .
[8] Ellis Horowitz,et al. Abstract data types and software validation , 1978, CACM.
[9] L. C.NorrisIpDavid,et al. Better Veri cation Through Symmetry , 1996 .
[10] Andreas J. Drexler,et al. Higher-Level Speci cation and Veri cationWith BDDs ? , 1992 .
[11] Pierre Wolper,et al. Memory-efficient algorithms for the verification of temporal properties , 1990, Formal Methods Syst. Des..
[12] Alberto L. Sangiovanni-Vincentelli,et al. On the Automatic Computation of Network Invariants , 1994, CAV.
[13] Ganesh Gopalakrishnan,et al. Design and Evaluation of the Rollback Chip: Special Purpose Hardware for Time Warp , 1992, IEEE Trans. Computers.
[14] Ganesh Gopalakrishnan,et al. Design and verification of the Rollback Chip using HOP: a case study of formal methods applied to hardware design , 1993, TOCS.
[15] Sérgio Vale Aguiar Campos,et al. Symbolic Model Checking , 1993, CAV.