An integrated 2D systolic array for spelling correction

Abstract This paper introduces a fully integrated spelling co-processor for speeding up the character string comparison process. The chip we present is architectured around a truncated 2-D systolic array of 69 processors and is able to process more than 2 million of words per second. The high regularity of the chip has been exploited for investigating a design methodology based on the automated generation of a representative subcircuit: the kernel.