Automatic Synthesis of Extended Burst-Mode Circuits : Part II ( Automatic Synthesis )

We introduce a new design style calledextended burst-mode . The extended burst-mode design style covers a wide spectrum of sequential circuits ranging from delay-insensitive to synchronous. We can synthesize multiple-input change asynchronous finite state machi nes, and many circuits that fall in the gray area (hard to classify as synchronous or asynchronous) which are difficult or impossible to synthesize au tomatically using existing methods. Our implementation of extended burst -mode machines uses standard CMOS logic, generates low-latency out p ts, and guarantees freedom from hazards at the gate level. In Part II, we p resent a complete set of automated sequential synthesis algorithms: ha z rd-free state assignment, hazard-free state minimization, and critical -race-free state encoding. Experimental data from a large set of examples are pr esented and compared to competing methods, whenever possible. Keywords— Asynchronous controller, Extended burst-mode, Automati c synthesis

[1]  James H. Tracey Internal State Assignments for Asynchronous Sequential Machines , 1966, IEEE Trans. Electron. Comput..

[2]  Stephen H. Unger,et al.  Asynchronous sequential switching circuits , 1969 .

[3]  Edward J. McCluskey,et al.  Logic design principles - with emphasis on testable semicustom circuits , 1986, Prentice Hall series in computer engineering.

[4]  Marly Roncken,et al.  The VLSI-programming language Tangram and its translation into handshake circuits , 1991, Proceedings of the European Conference on Design Automation..

[5]  David L. Dill,et al.  Automatic synthesis of locally-clocked asynchronous state machines , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[6]  Kenneth Y. Yun,et al.  Automatic synthesis of 3D asynchronous state machines , 1992, ICCAD.

[7]  Kenneth Y. Yun,et al.  Practical asynchronous controller design , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[8]  Teresa H. Y. Meng,et al.  Synthesis of Timed Asynchronous CircuitsChris , 1993 .

[9]  Mark E. Dean,et al.  The design of a high-performance cache controller: a case study in asynchronous synthesis , 1993, Integr..

[10]  Steven M. Nowick,et al.  Automatic synthesis of burst-mode asynchronous controllers , 1993 .

[11]  Alan Marshall,et al.  Designing an asynchronous communications chip , 1994, IEEE Design & Test of Computers.

[12]  Hugo De Man,et al.  Assassin: a synthesis system for asynchronous control circuits , 1994 .

[13]  Symbolic hazard-free minimization and encoding of asynchronous finite state machines , 1995, ICCAD.

[14]  A.L. Sangiovanni-Vincentelli,et al.  Synthesis of hazard-free asynchronous circuits with bounded wire delays , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Kenneth Y. Yun,et al.  A high-performance asynchronous SCSI controller , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[16]  David L. Dill,et al.  Exact two-level minimization of hazard-free logic with multiple-input changes , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Polly Sara Kay Siegel,et al.  Automatic Technology Mapping for Asynchronous Designs , 1995 .

[18]  Luciano Lavagno,et al.  Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .

[19]  Peter A. Beerel,et al.  The design and verification of a high-performance low-control-overhead asynchronous differential equation solver , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[20]  Kenneth Y. Yun,et al.  Timing analysis for extended burst-mode circuits , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.