Single Core Hardware Module to Implement Boolean Function Classification Techniques

Problem statement: Boolean function classification plays an important role in the field like technology mapping for digital circuit design, function mapping for minimization and the development of universal logic modules. Approach: In this study, we present a single core hardware module to implement Boolean function classification techniques on Altera FLEX10K FPGA device for lossless data compression. The compression algorithm was performed by incorporating Boolean function classification into Huffman coding. This allows compression that was more efficient because the data had been categorized and simplified before the encoding was done. Simulation, timing analysis and circuit synthesis were commenced to verify the functionality and performance of the designated circuits which supports the practicality, advantages and effectiveness of the proposed single core hardware implementation. Results: The result shows a higher compression ratio. The average compression ratio was 25-37.5% from numerous testing with various text inputs with a maximum clock frequency of 27.9 MHz. Conclusion: The hardware implementation demonstrated complete, correct functionality and met all the initial system requirements.

[1]  Masaru Kamada,et al.  Time-stamp service makes real-time gaming cheat-free , 2007, NetGames '07.

[2]  Faisal Mohd-Yasin,et al.  Design and Implementation of a Data Compression Scheme: A Partial Matching Approach , 2006, International Conference on Computer Graphics, Imaging and Visualisation (CGIV'06).

[3]  Faisal Mohd-Yasin,et al.  VHDL Modeling for Classification of Power Quality Disturbance Employing Wavelet Transform, Artificial Neural Network and Fuzzy Logic , 2006, Simul..

[4]  Malgorzata Marek-Sadowska,et al.  Boolean Functions Classification via Fixed Polarity Reed-Muller Forms , 1997, IEEE Trans. Computers.

[5]  Faisal Mohd-Yasin,et al.  Power quality disturbance detection using artificial intelligence: a hardware approach , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

[6]  Sanjeev R. Kulkarni,et al.  Universal coding of nonstationary sources , 2000, IEEE Trans. Inf. Theory.

[7]  M.I. Reaz,et al.  The FPGA prototyping of iris recognition for biometric identification employing neural network , 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..

[8]  F.M. Yasin,et al.  Iris recognition using neural network based on VHDL prototyping , 2004, Proceedings. 2004 International Conference on Information and Communication Technologies: From Theory to Applications, 2004..

[9]  Hasan Sarwar,et al.  FPGA realization of multipurpose FIR filter , 2003, Proceedings of the Fourth International Conference on Parallel and Distributed Computing, Applications and Technologies.

[10]  Daniel Gajski,et al.  Introduction to high-level synthesis , 1994, IEEE Design & Test of Computers.

[11]  Chip-Hong Chang,et al.  Operations on Boolean functions and variables in spectral domain of arithmetic transform , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[12]  Md. Mamun Ibne Reaz,et al.  Single core hardware module to implement encryption in TECB mode , 2007 .

[13]  R. D. M Hunter,et al.  Introduction to VHDL , 1996 .

[14]  Mamun Bin Ibne Reaz,et al.  Subway Train Braking System: A Fuzzy Based Hardware Approach , 2011 .

[15]  M. B. I. Reaz,et al.  Hardware prototyping of an intelligent current dq PI controller for FOC PMSM drive , 2010, International Conference on Electrical & Computer Engineering (ICECE 2010).

[16]  Peter J. Ashenden,et al.  The Designer's Guide to VHDL , 1995 .

[17]  Mamun Bin Ibne Reaz,et al.  Single core hardware module to implement partial encryption of compressed image , 2011 .

[18]  Md. Mamun Ibne Reaz,et al.  Prototyping of Wavelet Transform, Artificial Neural Network and Fuzzy Logic for Power Quality Disturbance Classifier , 2007 .

[19]  David A. Huffman,et al.  A method for the construction of minimum-redundancy codes , 1952, Proceedings of the IRE.

[20]  M. B. I. Reaz,et al.  Hardware implementations of an image compressor for mobile communications , 2008 .

[21]  Daniel Gajski,et al.  An Introduction to High-Level Synthesis , 2009, IEEE Design & Test of Computers.

[22]  Md. Syedul Amin,et al.  Design and implementation of novel artificial neural network based stock market forecasting system on field-programmable gate arrays , 2011 .

[23]  Faisal Mohd-Yasin,et al.  Partial encryption of compressed images employing FPGA , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[24]  Tom Chen,et al.  Design and implementation , 2006, IEEE Commun. Mag..

[25]  Jiqiang Zhai,et al.  Design and Implementation , 2011 .